
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Mon Feb  5 07:30:48 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fnmadd.s.cgf \
 \
//                  -- xlen 64  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmadd.s instruction of the RISC-V RV64_Zfinx,RV64_Zdinx extension for the fnmadd_b15 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64I_Zfinx,RV64I_Zdinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*);def TEST_CASE_1=True;",fnmadd_b15)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_3835:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8c80ffff; valaddr_reg:x12; val_offset:11442*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11442*FLEN/8, x13, x9, x10)

inst_3836:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8cff8000; valaddr_reg:x12; val_offset:11445*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11445*FLEN/8, x13, x9, x10)

inst_3837:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8c807fff; valaddr_reg:x12; val_offset:11448*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11448*FLEN/8, x13, x9, x10)

inst_3838:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8cffc000; valaddr_reg:x12; val_offset:11451*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11451*FLEN/8, x13, x9, x10)

inst_3839:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8c803fff; valaddr_reg:x12; val_offset:11454*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11454*FLEN/8, x13, x9, x10)

inst_3840:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8cffe000; valaddr_reg:x12; val_offset:11457*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11457*FLEN/8, x13, x9, x10)

inst_3841:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8c801fff; valaddr_reg:x12; val_offset:11460*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11460*FLEN/8, x13, x9, x10)

inst_3842:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8cfff000; valaddr_reg:x12; val_offset:11463*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11463*FLEN/8, x13, x9, x10)

inst_3843:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8c800fff; valaddr_reg:x12; val_offset:11466*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11466*FLEN/8, x13, x9, x10)

inst_3844:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8cfff800; valaddr_reg:x12; val_offset:11469*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11469*FLEN/8, x13, x9, x10)

inst_3845:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8c8007ff; valaddr_reg:x12; val_offset:11472*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11472*FLEN/8, x13, x9, x10)

inst_3846:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8cfffc00; valaddr_reg:x12; val_offset:11475*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11475*FLEN/8, x13, x9, x10)

inst_3847:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8c8003ff; valaddr_reg:x12; val_offset:11478*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11478*FLEN/8, x13, x9, x10)

inst_3848:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8cfffe00; valaddr_reg:x12; val_offset:11481*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11481*FLEN/8, x13, x9, x10)

inst_3849:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8c8001ff; valaddr_reg:x12; val_offset:11484*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11484*FLEN/8, x13, x9, x10)

inst_3850:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8cffff00; valaddr_reg:x12; val_offset:11487*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11487*FLEN/8, x13, x9, x10)

inst_3851:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8c8000ff; valaddr_reg:x12; val_offset:11490*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11490*FLEN/8, x13, x9, x10)

inst_3852:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8cffff80; valaddr_reg:x12; val_offset:11493*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11493*FLEN/8, x13, x9, x10)

inst_3853:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8c80007f; valaddr_reg:x12; val_offset:11496*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11496*FLEN/8, x13, x9, x10)

inst_3854:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8cffffc0; valaddr_reg:x12; val_offset:11499*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11499*FLEN/8, x13, x9, x10)

inst_3855:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8c80003f; valaddr_reg:x12; val_offset:11502*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11502*FLEN/8, x13, x9, x10)

inst_3856:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8cffffe0; valaddr_reg:x12; val_offset:11505*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11505*FLEN/8, x13, x9, x10)

inst_3857:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8c80001f; valaddr_reg:x12; val_offset:11508*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11508*FLEN/8, x13, x9, x10)

inst_3858:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8cfffff0; valaddr_reg:x12; val_offset:11511*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11511*FLEN/8, x13, x9, x10)

inst_3859:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8c80000f; valaddr_reg:x12; val_offset:11514*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11514*FLEN/8, x13, x9, x10)

inst_3860:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8cfffff8; valaddr_reg:x12; val_offset:11517*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11517*FLEN/8, x13, x9, x10)

inst_3861:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8c800007; valaddr_reg:x12; val_offset:11520*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11520*FLEN/8, x13, x9, x10)

inst_3862:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8cfffffc; valaddr_reg:x12; val_offset:11523*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11523*FLEN/8, x13, x9, x10)

inst_3863:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8c800003; valaddr_reg:x12; val_offset:11526*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11526*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_30)
inst_3864:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8cfffffe; valaddr_reg:x12; val_offset:11529*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11529*FLEN/8, x13, x9, x10)

inst_3865:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8c800001; valaddr_reg:x12; val_offset:11532*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11532*FLEN/8, x13, x9, x10)

inst_3866:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x12; val_offset:11535*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11535*FLEN/8, x13, x9, x10)

inst_3867:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x12; val_offset:11538*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11538*FLEN/8, x13, x9, x10)

inst_3868:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x12; val_offset:11541*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11541*FLEN/8, x13, x9, x10)

inst_3869:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x12; val_offset:11544*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11544*FLEN/8, x13, x9, x10)

inst_3870:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:11547*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11547*FLEN/8, x13, x9, x10)

inst_3871:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:11550*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11550*FLEN/8, x13, x9, x10)

inst_3872:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x12; val_offset:11553*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11553*FLEN/8, x13, x9, x10)

inst_3873:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x12; val_offset:11556*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11556*FLEN/8, x13, x9, x10)

inst_3874:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x12; val_offset:11559*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11559*FLEN/8, x13, x9, x10)

inst_3875:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x12; val_offset:11562*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11562*FLEN/8, x13, x9, x10)

inst_3876:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x12; val_offset:11565*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11565*FLEN/8, x13, x9, x10)

inst_3877:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x12; val_offset:11568*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11568*FLEN/8, x13, x9, x10)

inst_3878:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x12; val_offset:11571*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11571*FLEN/8, x13, x9, x10)

inst_3879:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x12; val_offset:11574*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11574*FLEN/8, x13, x9, x10)

inst_3880:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x12; val_offset:11577*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11577*FLEN/8, x13, x9, x10)

inst_3881:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0dbcc3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0dbcc3; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x12; val_offset:11580*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11580*FLEN/8, x13, x9, x10)

inst_3882:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d000000; valaddr_reg:x12; val_offset:11583*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11583*FLEN/8, x13, x9, x10)

inst_3883:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7fffff; valaddr_reg:x12; val_offset:11586*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11586*FLEN/8, x13, x9, x10)

inst_3884:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d400000; valaddr_reg:x12; val_offset:11589*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11589*FLEN/8, x13, x9, x10)

inst_3885:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d3fffff; valaddr_reg:x12; val_offset:11592*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11592*FLEN/8, x13, x9, x10)

inst_3886:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d600000; valaddr_reg:x12; val_offset:11595*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11595*FLEN/8, x13, x9, x10)

inst_3887:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d1fffff; valaddr_reg:x12; val_offset:11598*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11598*FLEN/8, x13, x9, x10)

inst_3888:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d700000; valaddr_reg:x12; val_offset:11601*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11601*FLEN/8, x13, x9, x10)

inst_3889:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d0fffff; valaddr_reg:x12; val_offset:11604*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11604*FLEN/8, x13, x9, x10)

inst_3890:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d780000; valaddr_reg:x12; val_offset:11607*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11607*FLEN/8, x13, x9, x10)

inst_3891:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d07ffff; valaddr_reg:x12; val_offset:11610*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11610*FLEN/8, x13, x9, x10)

inst_3892:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7c0000; valaddr_reg:x12; val_offset:11613*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11613*FLEN/8, x13, x9, x10)

inst_3893:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d03ffff; valaddr_reg:x12; val_offset:11616*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11616*FLEN/8, x13, x9, x10)

inst_3894:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7e0000; valaddr_reg:x12; val_offset:11619*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11619*FLEN/8, x13, x9, x10)

inst_3895:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d01ffff; valaddr_reg:x12; val_offset:11622*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11622*FLEN/8, x13, x9, x10)

inst_3896:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7f0000; valaddr_reg:x12; val_offset:11625*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11625*FLEN/8, x13, x9, x10)

inst_3897:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d00ffff; valaddr_reg:x12; val_offset:11628*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11628*FLEN/8, x13, x9, x10)

inst_3898:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7f8000; valaddr_reg:x12; val_offset:11631*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11631*FLEN/8, x13, x9, x10)

inst_3899:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d007fff; valaddr_reg:x12; val_offset:11634*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11634*FLEN/8, x13, x9, x10)

inst_3900:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7fc000; valaddr_reg:x12; val_offset:11637*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11637*FLEN/8, x13, x9, x10)

inst_3901:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d003fff; valaddr_reg:x12; val_offset:11640*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11640*FLEN/8, x13, x9, x10)

inst_3902:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7fe000; valaddr_reg:x12; val_offset:11643*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11643*FLEN/8, x13, x9, x10)

inst_3903:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d001fff; valaddr_reg:x12; val_offset:11646*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11646*FLEN/8, x13, x9, x10)

inst_3904:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7ff000; valaddr_reg:x12; val_offset:11649*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11649*FLEN/8, x13, x9, x10)

inst_3905:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d000fff; valaddr_reg:x12; val_offset:11652*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11652*FLEN/8, x13, x9, x10)

inst_3906:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7ff800; valaddr_reg:x12; val_offset:11655*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11655*FLEN/8, x13, x9, x10)

inst_3907:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d0007ff; valaddr_reg:x12; val_offset:11658*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11658*FLEN/8, x13, x9, x10)

inst_3908:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7ffc00; valaddr_reg:x12; val_offset:11661*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11661*FLEN/8, x13, x9, x10)

inst_3909:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d0003ff; valaddr_reg:x12; val_offset:11664*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11664*FLEN/8, x13, x9, x10)

inst_3910:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7ffe00; valaddr_reg:x12; val_offset:11667*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11667*FLEN/8, x13, x9, x10)

inst_3911:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d0001ff; valaddr_reg:x12; val_offset:11670*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11670*FLEN/8, x13, x9, x10)

inst_3912:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7fff00; valaddr_reg:x12; val_offset:11673*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11673*FLEN/8, x13, x9, x10)

inst_3913:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d0000ff; valaddr_reg:x12; val_offset:11676*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11676*FLEN/8, x13, x9, x10)

inst_3914:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7fff80; valaddr_reg:x12; val_offset:11679*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11679*FLEN/8, x13, x9, x10)

inst_3915:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d00007f; valaddr_reg:x12; val_offset:11682*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11682*FLEN/8, x13, x9, x10)

inst_3916:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7fffc0; valaddr_reg:x12; val_offset:11685*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11685*FLEN/8, x13, x9, x10)

inst_3917:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d00003f; valaddr_reg:x12; val_offset:11688*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11688*FLEN/8, x13, x9, x10)

inst_3918:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7fffe0; valaddr_reg:x12; val_offset:11691*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11691*FLEN/8, x13, x9, x10)

inst_3919:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d00001f; valaddr_reg:x12; val_offset:11694*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11694*FLEN/8, x13, x9, x10)

inst_3920:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7ffff0; valaddr_reg:x12; val_offset:11697*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11697*FLEN/8, x13, x9, x10)

inst_3921:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d00000f; valaddr_reg:x12; val_offset:11700*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11700*FLEN/8, x13, x9, x10)

inst_3922:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7ffff8; valaddr_reg:x12; val_offset:11703*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11703*FLEN/8, x13, x9, x10)

inst_3923:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d000007; valaddr_reg:x12; val_offset:11706*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11706*FLEN/8, x13, x9, x10)

inst_3924:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7ffffc; valaddr_reg:x12; val_offset:11709*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11709*FLEN/8, x13, x9, x10)

inst_3925:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d000003; valaddr_reg:x12; val_offset:11712*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11712*FLEN/8, x13, x9, x10)

inst_3926:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d7ffffe; valaddr_reg:x12; val_offset:11715*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11715*FLEN/8, x13, x9, x10)

inst_3927:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8d000001; valaddr_reg:x12; val_offset:11718*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11718*FLEN/8, x13, x9, x10)

inst_3928:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x12; val_offset:11721*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11721*FLEN/8, x13, x9, x10)

inst_3929:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x12; val_offset:11724*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11724*FLEN/8, x13, x9, x10)

inst_3930:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x12; val_offset:11727*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11727*FLEN/8, x13, x9, x10)

inst_3931:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x12; val_offset:11730*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11730*FLEN/8, x13, x9, x10)

inst_3932:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:11733*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11733*FLEN/8, x13, x9, x10)

inst_3933:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:11736*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11736*FLEN/8, x13, x9, x10)

inst_3934:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x12; val_offset:11739*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11739*FLEN/8, x13, x9, x10)

inst_3935:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x12; val_offset:11742*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11742*FLEN/8, x13, x9, x10)

inst_3936:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x12; val_offset:11745*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11745*FLEN/8, x13, x9, x10)

inst_3937:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x12; val_offset:11748*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11748*FLEN/8, x13, x9, x10)

inst_3938:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x12; val_offset:11751*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11751*FLEN/8, x13, x9, x10)

inst_3939:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x12; val_offset:11754*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11754*FLEN/8, x13, x9, x10)

inst_3940:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x12; val_offset:11757*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11757*FLEN/8, x13, x9, x10)

inst_3941:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x12; val_offset:11760*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11760*FLEN/8, x13, x9, x10)

inst_3942:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x12; val_offset:11763*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11763*FLEN/8, x13, x9, x10)

inst_3943:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x04d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d84d070; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x12; val_offset:11766*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11766*FLEN/8, x13, x9, x10)

inst_3944:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d800000; valaddr_reg:x12; val_offset:11769*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11769*FLEN/8, x13, x9, x10)

inst_3945:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dffffff; valaddr_reg:x12; val_offset:11772*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11772*FLEN/8, x13, x9, x10)

inst_3946:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dc00000; valaddr_reg:x12; val_offset:11775*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11775*FLEN/8, x13, x9, x10)

inst_3947:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dbfffff; valaddr_reg:x12; val_offset:11778*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11778*FLEN/8, x13, x9, x10)

inst_3948:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8de00000; valaddr_reg:x12; val_offset:11781*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11781*FLEN/8, x13, x9, x10)

inst_3949:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d9fffff; valaddr_reg:x12; val_offset:11784*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11784*FLEN/8, x13, x9, x10)

inst_3950:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8df00000; valaddr_reg:x12; val_offset:11787*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11787*FLEN/8, x13, x9, x10)

inst_3951:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d8fffff; valaddr_reg:x12; val_offset:11790*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11790*FLEN/8, x13, x9, x10)

inst_3952:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8df80000; valaddr_reg:x12; val_offset:11793*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11793*FLEN/8, x13, x9, x10)

inst_3953:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d87ffff; valaddr_reg:x12; val_offset:11796*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11796*FLEN/8, x13, x9, x10)

inst_3954:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dfc0000; valaddr_reg:x12; val_offset:11799*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11799*FLEN/8, x13, x9, x10)

inst_3955:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d83ffff; valaddr_reg:x12; val_offset:11802*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11802*FLEN/8, x13, x9, x10)

inst_3956:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dfe0000; valaddr_reg:x12; val_offset:11805*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11805*FLEN/8, x13, x9, x10)

inst_3957:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d81ffff; valaddr_reg:x12; val_offset:11808*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11808*FLEN/8, x13, x9, x10)

inst_3958:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dff0000; valaddr_reg:x12; val_offset:11811*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11811*FLEN/8, x13, x9, x10)

inst_3959:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d80ffff; valaddr_reg:x12; val_offset:11814*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11814*FLEN/8, x13, x9, x10)

inst_3960:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dff8000; valaddr_reg:x12; val_offset:11817*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11817*FLEN/8, x13, x9, x10)

inst_3961:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d807fff; valaddr_reg:x12; val_offset:11820*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11820*FLEN/8, x13, x9, x10)

inst_3962:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dffc000; valaddr_reg:x12; val_offset:11823*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11823*FLEN/8, x13, x9, x10)

inst_3963:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d803fff; valaddr_reg:x12; val_offset:11826*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11826*FLEN/8, x13, x9, x10)

inst_3964:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dffe000; valaddr_reg:x12; val_offset:11829*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11829*FLEN/8, x13, x9, x10)

inst_3965:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d801fff; valaddr_reg:x12; val_offset:11832*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11832*FLEN/8, x13, x9, x10)

inst_3966:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dfff000; valaddr_reg:x12; val_offset:11835*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11835*FLEN/8, x13, x9, x10)

inst_3967:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d800fff; valaddr_reg:x12; val_offset:11838*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11838*FLEN/8, x13, x9, x10)

inst_3968:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dfff800; valaddr_reg:x12; val_offset:11841*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11841*FLEN/8, x13, x9, x10)

inst_3969:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d8007ff; valaddr_reg:x12; val_offset:11844*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11844*FLEN/8, x13, x9, x10)

inst_3970:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dfffc00; valaddr_reg:x12; val_offset:11847*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11847*FLEN/8, x13, x9, x10)

inst_3971:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d8003ff; valaddr_reg:x12; val_offset:11850*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11850*FLEN/8, x13, x9, x10)

inst_3972:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dfffe00; valaddr_reg:x12; val_offset:11853*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11853*FLEN/8, x13, x9, x10)

inst_3973:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d8001ff; valaddr_reg:x12; val_offset:11856*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11856*FLEN/8, x13, x9, x10)

inst_3974:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dffff00; valaddr_reg:x12; val_offset:11859*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11859*FLEN/8, x13, x9, x10)

inst_3975:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d8000ff; valaddr_reg:x12; val_offset:11862*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11862*FLEN/8, x13, x9, x10)

inst_3976:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dffff80; valaddr_reg:x12; val_offset:11865*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11865*FLEN/8, x13, x9, x10)

inst_3977:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d80007f; valaddr_reg:x12; val_offset:11868*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11868*FLEN/8, x13, x9, x10)

inst_3978:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dffffc0; valaddr_reg:x12; val_offset:11871*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11871*FLEN/8, x13, x9, x10)

inst_3979:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d80003f; valaddr_reg:x12; val_offset:11874*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11874*FLEN/8, x13, x9, x10)

inst_3980:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dffffe0; valaddr_reg:x12; val_offset:11877*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11877*FLEN/8, x13, x9, x10)

inst_3981:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d80001f; valaddr_reg:x12; val_offset:11880*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11880*FLEN/8, x13, x9, x10)

inst_3982:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dfffff0; valaddr_reg:x12; val_offset:11883*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11883*FLEN/8, x13, x9, x10)

inst_3983:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d80000f; valaddr_reg:x12; val_offset:11886*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11886*FLEN/8, x13, x9, x10)

inst_3984:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dfffff8; valaddr_reg:x12; val_offset:11889*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11889*FLEN/8, x13, x9, x10)

inst_3985:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d800007; valaddr_reg:x12; val_offset:11892*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11892*FLEN/8, x13, x9, x10)

inst_3986:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dfffffc; valaddr_reg:x12; val_offset:11895*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11895*FLEN/8, x13, x9, x10)

inst_3987:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d800003; valaddr_reg:x12; val_offset:11898*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11898*FLEN/8, x13, x9, x10)

inst_3988:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8dfffffe; valaddr_reg:x12; val_offset:11901*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11901*FLEN/8, x13, x9, x10)

inst_3989:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8d800001; valaddr_reg:x12; val_offset:11904*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11904*FLEN/8, x13, x9, x10)

inst_3990:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x12; val_offset:11907*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11907*FLEN/8, x13, x9, x10)

inst_3991:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x12; val_offset:11910*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11910*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_31)
inst_3992:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x12; val_offset:11913*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11913*FLEN/8, x13, x9, x10)

inst_3993:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x12; val_offset:11916*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11916*FLEN/8, x13, x9, x10)

inst_3994:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:11919*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11919*FLEN/8, x13, x9, x10)

inst_3995:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:11922*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11922*FLEN/8, x13, x9, x10)

inst_3996:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x12; val_offset:11925*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11925*FLEN/8, x13, x9, x10)

inst_3997:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x12; val_offset:11928*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11928*FLEN/8, x13, x9, x10)

inst_3998:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x12; val_offset:11931*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11931*FLEN/8, x13, x9, x10)

inst_3999:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x12; val_offset:11934*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11934*FLEN/8, x13, x9, x10)

inst_4000:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x12; val_offset:11937*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11937*FLEN/8, x13, x9, x10)

inst_4001:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x12; val_offset:11940*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11940*FLEN/8, x13, x9, x10)

inst_4002:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x12; val_offset:11943*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11943*FLEN/8, x13, x9, x10)

inst_4003:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x12; val_offset:11946*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11946*FLEN/8, x13, x9, x10)

inst_4004:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x12; val_offset:11949*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11949*FLEN/8, x13, x9, x10)

inst_4005:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ee20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efee20b; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x12; val_offset:11952*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11952*FLEN/8, x13, x9, x10)

inst_4006:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e000000; valaddr_reg:x12; val_offset:11955*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11955*FLEN/8, x13, x9, x10)

inst_4007:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7fffff; valaddr_reg:x12; val_offset:11958*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11958*FLEN/8, x13, x9, x10)

inst_4008:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e400000; valaddr_reg:x12; val_offset:11961*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11961*FLEN/8, x13, x9, x10)

inst_4009:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e3fffff; valaddr_reg:x12; val_offset:11964*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11964*FLEN/8, x13, x9, x10)

inst_4010:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e600000; valaddr_reg:x12; val_offset:11967*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11967*FLEN/8, x13, x9, x10)

inst_4011:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e1fffff; valaddr_reg:x12; val_offset:11970*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11970*FLEN/8, x13, x9, x10)

inst_4012:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e700000; valaddr_reg:x12; val_offset:11973*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11973*FLEN/8, x13, x9, x10)

inst_4013:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e0fffff; valaddr_reg:x12; val_offset:11976*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11976*FLEN/8, x13, x9, x10)

inst_4014:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e780000; valaddr_reg:x12; val_offset:11979*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11979*FLEN/8, x13, x9, x10)

inst_4015:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e07ffff; valaddr_reg:x12; val_offset:11982*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11982*FLEN/8, x13, x9, x10)

inst_4016:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7c0000; valaddr_reg:x12; val_offset:11985*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11985*FLEN/8, x13, x9, x10)

inst_4017:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e03ffff; valaddr_reg:x12; val_offset:11988*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11988*FLEN/8, x13, x9, x10)

inst_4018:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7e0000; valaddr_reg:x12; val_offset:11991*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11991*FLEN/8, x13, x9, x10)

inst_4019:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e01ffff; valaddr_reg:x12; val_offset:11994*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11994*FLEN/8, x13, x9, x10)

inst_4020:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7f0000; valaddr_reg:x12; val_offset:11997*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11997*FLEN/8, x13, x9, x10)

inst_4021:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e00ffff; valaddr_reg:x12; val_offset:12000*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12000*FLEN/8, x13, x9, x10)

inst_4022:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7f8000; valaddr_reg:x12; val_offset:12003*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12003*FLEN/8, x13, x9, x10)

inst_4023:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e007fff; valaddr_reg:x12; val_offset:12006*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12006*FLEN/8, x13, x9, x10)

inst_4024:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7fc000; valaddr_reg:x12; val_offset:12009*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12009*FLEN/8, x13, x9, x10)

inst_4025:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e003fff; valaddr_reg:x12; val_offset:12012*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12012*FLEN/8, x13, x9, x10)

inst_4026:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7fe000; valaddr_reg:x12; val_offset:12015*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12015*FLEN/8, x13, x9, x10)

inst_4027:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e001fff; valaddr_reg:x12; val_offset:12018*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12018*FLEN/8, x13, x9, x10)

inst_4028:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7ff000; valaddr_reg:x12; val_offset:12021*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12021*FLEN/8, x13, x9, x10)

inst_4029:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e000fff; valaddr_reg:x12; val_offset:12024*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12024*FLEN/8, x13, x9, x10)

inst_4030:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7ff800; valaddr_reg:x12; val_offset:12027*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12027*FLEN/8, x13, x9, x10)

inst_4031:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e0007ff; valaddr_reg:x12; val_offset:12030*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12030*FLEN/8, x13, x9, x10)

inst_4032:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7ffc00; valaddr_reg:x12; val_offset:12033*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12033*FLEN/8, x13, x9, x10)

inst_4033:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e0003ff; valaddr_reg:x12; val_offset:12036*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12036*FLEN/8, x13, x9, x10)

inst_4034:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7ffe00; valaddr_reg:x12; val_offset:12039*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12039*FLEN/8, x13, x9, x10)

inst_4035:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e0001ff; valaddr_reg:x12; val_offset:12042*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12042*FLEN/8, x13, x9, x10)

inst_4036:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7fff00; valaddr_reg:x12; val_offset:12045*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12045*FLEN/8, x13, x9, x10)

inst_4037:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e0000ff; valaddr_reg:x12; val_offset:12048*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12048*FLEN/8, x13, x9, x10)

inst_4038:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7fff80; valaddr_reg:x12; val_offset:12051*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12051*FLEN/8, x13, x9, x10)

inst_4039:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e00007f; valaddr_reg:x12; val_offset:12054*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12054*FLEN/8, x13, x9, x10)

inst_4040:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7fffc0; valaddr_reg:x12; val_offset:12057*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12057*FLEN/8, x13, x9, x10)

inst_4041:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e00003f; valaddr_reg:x12; val_offset:12060*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12060*FLEN/8, x13, x9, x10)

inst_4042:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7fffe0; valaddr_reg:x12; val_offset:12063*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12063*FLEN/8, x13, x9, x10)

inst_4043:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e00001f; valaddr_reg:x12; val_offset:12066*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12066*FLEN/8, x13, x9, x10)

inst_4044:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7ffff0; valaddr_reg:x12; val_offset:12069*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12069*FLEN/8, x13, x9, x10)

inst_4045:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e00000f; valaddr_reg:x12; val_offset:12072*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12072*FLEN/8, x13, x9, x10)

inst_4046:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7ffff8; valaddr_reg:x12; val_offset:12075*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12075*FLEN/8, x13, x9, x10)

inst_4047:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e000007; valaddr_reg:x12; val_offset:12078*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12078*FLEN/8, x13, x9, x10)

inst_4048:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7ffffc; valaddr_reg:x12; val_offset:12081*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12081*FLEN/8, x13, x9, x10)

inst_4049:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e000003; valaddr_reg:x12; val_offset:12084*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12084*FLEN/8, x13, x9, x10)

inst_4050:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e7ffffe; valaddr_reg:x12; val_offset:12087*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12087*FLEN/8, x13, x9, x10)

inst_4051:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1c and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8e000001; valaddr_reg:x12; val_offset:12090*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12090*FLEN/8, x13, x9, x10)

inst_4052:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x12; val_offset:12093*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12093*FLEN/8, x13, x9, x10)

inst_4053:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x12; val_offset:12096*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12096*FLEN/8, x13, x9, x10)

inst_4054:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x12; val_offset:12099*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12099*FLEN/8, x13, x9, x10)

inst_4055:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x12; val_offset:12102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12102*FLEN/8, x13, x9, x10)

inst_4056:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12105*FLEN/8, x13, x9, x10)

inst_4057:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:12108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12108*FLEN/8, x13, x9, x10)

inst_4058:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x12; val_offset:12111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12111*FLEN/8, x13, x9, x10)

inst_4059:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x12; val_offset:12114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12114*FLEN/8, x13, x9, x10)

inst_4060:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x12; val_offset:12117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12117*FLEN/8, x13, x9, x10)

inst_4061:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x12; val_offset:12120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12120*FLEN/8, x13, x9, x10)

inst_4062:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x12; val_offset:12123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12123*FLEN/8, x13, x9, x10)

inst_4063:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x12; val_offset:12126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12126*FLEN/8, x13, x9, x10)

inst_4064:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x12; val_offset:12129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12129*FLEN/8, x13, x9, x10)

inst_4065:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x12; val_offset:12132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12132*FLEN/8, x13, x9, x10)

inst_4066:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x12; val_offset:12135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12135*FLEN/8, x13, x9, x10)

inst_4067:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x25c84c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7da5c84c; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x12; val_offset:12138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12138*FLEN/8, x13, x9, x10)

inst_4068:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e800000; valaddr_reg:x12; val_offset:12141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12141*FLEN/8, x13, x9, x10)

inst_4069:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8effffff; valaddr_reg:x12; val_offset:12144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12144*FLEN/8, x13, x9, x10)

inst_4070:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8ec00000; valaddr_reg:x12; val_offset:12147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12147*FLEN/8, x13, x9, x10)

inst_4071:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8ebfffff; valaddr_reg:x12; val_offset:12150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12150*FLEN/8, x13, x9, x10)

inst_4072:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8ee00000; valaddr_reg:x12; val_offset:12153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12153*FLEN/8, x13, x9, x10)

inst_4073:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e9fffff; valaddr_reg:x12; val_offset:12156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12156*FLEN/8, x13, x9, x10)

inst_4074:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8ef00000; valaddr_reg:x12; val_offset:12159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12159*FLEN/8, x13, x9, x10)

inst_4075:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e8fffff; valaddr_reg:x12; val_offset:12162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12162*FLEN/8, x13, x9, x10)

inst_4076:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8ef80000; valaddr_reg:x12; val_offset:12165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12165*FLEN/8, x13, x9, x10)

inst_4077:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e87ffff; valaddr_reg:x12; val_offset:12168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12168*FLEN/8, x13, x9, x10)

inst_4078:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8efc0000; valaddr_reg:x12; val_offset:12171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12171*FLEN/8, x13, x9, x10)

inst_4079:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e83ffff; valaddr_reg:x12; val_offset:12174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12174*FLEN/8, x13, x9, x10)

inst_4080:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8efe0000; valaddr_reg:x12; val_offset:12177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12177*FLEN/8, x13, x9, x10)

inst_4081:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e81ffff; valaddr_reg:x12; val_offset:12180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12180*FLEN/8, x13, x9, x10)

inst_4082:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8eff0000; valaddr_reg:x12; val_offset:12183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12183*FLEN/8, x13, x9, x10)

inst_4083:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e80ffff; valaddr_reg:x12; val_offset:12186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12186*FLEN/8, x13, x9, x10)

inst_4084:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8eff8000; valaddr_reg:x12; val_offset:12189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12189*FLEN/8, x13, x9, x10)

inst_4085:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e807fff; valaddr_reg:x12; val_offset:12192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12192*FLEN/8, x13, x9, x10)

inst_4086:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8effc000; valaddr_reg:x12; val_offset:12195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12195*FLEN/8, x13, x9, x10)

inst_4087:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e803fff; valaddr_reg:x12; val_offset:12198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12198*FLEN/8, x13, x9, x10)

inst_4088:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8effe000; valaddr_reg:x12; val_offset:12201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12201*FLEN/8, x13, x9, x10)

inst_4089:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e801fff; valaddr_reg:x12; val_offset:12204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12204*FLEN/8, x13, x9, x10)

inst_4090:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8efff000; valaddr_reg:x12; val_offset:12207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12207*FLEN/8, x13, x9, x10)

inst_4091:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e800fff; valaddr_reg:x12; val_offset:12210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12210*FLEN/8, x13, x9, x10)

inst_4092:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8efff800; valaddr_reg:x12; val_offset:12213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12213*FLEN/8, x13, x9, x10)

inst_4093:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e8007ff; valaddr_reg:x12; val_offset:12216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12216*FLEN/8, x13, x9, x10)

inst_4094:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8efffc00; valaddr_reg:x12; val_offset:12219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12219*FLEN/8, x13, x9, x10)

inst_4095:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e8003ff; valaddr_reg:x12; val_offset:12222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12222*FLEN/8, x13, x9, x10)

inst_4096:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8efffe00; valaddr_reg:x12; val_offset:12225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12225*FLEN/8, x13, x9, x10)

inst_4097:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e8001ff; valaddr_reg:x12; val_offset:12228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12228*FLEN/8, x13, x9, x10)

inst_4098:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8effff00; valaddr_reg:x12; val_offset:12231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12231*FLEN/8, x13, x9, x10)

inst_4099:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e8000ff; valaddr_reg:x12; val_offset:12234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12234*FLEN/8, x13, x9, x10)

inst_4100:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8effff80; valaddr_reg:x12; val_offset:12237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12237*FLEN/8, x13, x9, x10)

inst_4101:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e80007f; valaddr_reg:x12; val_offset:12240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12240*FLEN/8, x13, x9, x10)

inst_4102:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8effffc0; valaddr_reg:x12; val_offset:12243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12243*FLEN/8, x13, x9, x10)

inst_4103:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e80003f; valaddr_reg:x12; val_offset:12246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12246*FLEN/8, x13, x9, x10)

inst_4104:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8effffe0; valaddr_reg:x12; val_offset:12249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12249*FLEN/8, x13, x9, x10)

inst_4105:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e80001f; valaddr_reg:x12; val_offset:12252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12252*FLEN/8, x13, x9, x10)

inst_4106:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8efffff0; valaddr_reg:x12; val_offset:12255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12255*FLEN/8, x13, x9, x10)

inst_4107:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e80000f; valaddr_reg:x12; val_offset:12258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12258*FLEN/8, x13, x9, x10)

inst_4108:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8efffff8; valaddr_reg:x12; val_offset:12261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12261*FLEN/8, x13, x9, x10)

inst_4109:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e800007; valaddr_reg:x12; val_offset:12264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12264*FLEN/8, x13, x9, x10)

inst_4110:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8efffffc; valaddr_reg:x12; val_offset:12267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12267*FLEN/8, x13, x9, x10)

inst_4111:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e800003; valaddr_reg:x12; val_offset:12270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12270*FLEN/8, x13, x9, x10)

inst_4112:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8efffffe; valaddr_reg:x12; val_offset:12273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12273*FLEN/8, x13, x9, x10)

inst_4113:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8e800001; valaddr_reg:x12; val_offset:12276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12276*FLEN/8, x13, x9, x10)

inst_4114:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x12; val_offset:12279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12279*FLEN/8, x13, x9, x10)

inst_4115:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x12; val_offset:12282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12282*FLEN/8, x13, x9, x10)

inst_4116:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x12; val_offset:12285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12285*FLEN/8, x13, x9, x10)

inst_4117:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x12; val_offset:12288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12288*FLEN/8, x13, x9, x10)

inst_4118:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12291*FLEN/8, x13, x9, x10)

inst_4119:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:12294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12294*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_32)
inst_4120:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x12; val_offset:12297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12297*FLEN/8, x13, x9, x10)

inst_4121:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x12; val_offset:12300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12300*FLEN/8, x13, x9, x10)

inst_4122:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x12; val_offset:12303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12303*FLEN/8, x13, x9, x10)

inst_4123:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x12; val_offset:12306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12306*FLEN/8, x13, x9, x10)

inst_4124:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x12; val_offset:12309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12309*FLEN/8, x13, x9, x10)

inst_4125:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x12; val_offset:12312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12312*FLEN/8, x13, x9, x10)

inst_4126:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x12; val_offset:12315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12315*FLEN/8, x13, x9, x10)

inst_4127:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x12; val_offset:12318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12318*FLEN/8, x13, x9, x10)

inst_4128:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x12; val_offset:12321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12321*FLEN/8, x13, x9, x10)

inst_4129:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7b70c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dfb70c9; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x12; val_offset:12324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12324*FLEN/8, x13, x9, x10)

inst_4130:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f000000; valaddr_reg:x12; val_offset:12327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12327*FLEN/8, x13, x9, x10)

inst_4131:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7fffff; valaddr_reg:x12; val_offset:12330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12330*FLEN/8, x13, x9, x10)

inst_4132:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f400000; valaddr_reg:x12; val_offset:12333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12333*FLEN/8, x13, x9, x10)

inst_4133:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f3fffff; valaddr_reg:x12; val_offset:12336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12336*FLEN/8, x13, x9, x10)

inst_4134:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f600000; valaddr_reg:x12; val_offset:12339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12339*FLEN/8, x13, x9, x10)

inst_4135:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f1fffff; valaddr_reg:x12; val_offset:12342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12342*FLEN/8, x13, x9, x10)

inst_4136:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f700000; valaddr_reg:x12; val_offset:12345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12345*FLEN/8, x13, x9, x10)

inst_4137:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f0fffff; valaddr_reg:x12; val_offset:12348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12348*FLEN/8, x13, x9, x10)

inst_4138:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f780000; valaddr_reg:x12; val_offset:12351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12351*FLEN/8, x13, x9, x10)

inst_4139:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f07ffff; valaddr_reg:x12; val_offset:12354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12354*FLEN/8, x13, x9, x10)

inst_4140:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7c0000; valaddr_reg:x12; val_offset:12357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12357*FLEN/8, x13, x9, x10)

inst_4141:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f03ffff; valaddr_reg:x12; val_offset:12360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12360*FLEN/8, x13, x9, x10)

inst_4142:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7e0000; valaddr_reg:x12; val_offset:12363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12363*FLEN/8, x13, x9, x10)

inst_4143:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f01ffff; valaddr_reg:x12; val_offset:12366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12366*FLEN/8, x13, x9, x10)

inst_4144:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7f0000; valaddr_reg:x12; val_offset:12369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12369*FLEN/8, x13, x9, x10)

inst_4145:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f00ffff; valaddr_reg:x12; val_offset:12372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12372*FLEN/8, x13, x9, x10)

inst_4146:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7f8000; valaddr_reg:x12; val_offset:12375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12375*FLEN/8, x13, x9, x10)

inst_4147:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f007fff; valaddr_reg:x12; val_offset:12378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12378*FLEN/8, x13, x9, x10)

inst_4148:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7fc000; valaddr_reg:x12; val_offset:12381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12381*FLEN/8, x13, x9, x10)

inst_4149:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f003fff; valaddr_reg:x12; val_offset:12384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12384*FLEN/8, x13, x9, x10)

inst_4150:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7fe000; valaddr_reg:x12; val_offset:12387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12387*FLEN/8, x13, x9, x10)

inst_4151:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f001fff; valaddr_reg:x12; val_offset:12390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12390*FLEN/8, x13, x9, x10)

inst_4152:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7ff000; valaddr_reg:x12; val_offset:12393*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12393*FLEN/8, x13, x9, x10)

inst_4153:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f000fff; valaddr_reg:x12; val_offset:12396*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12396*FLEN/8, x13, x9, x10)

inst_4154:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7ff800; valaddr_reg:x12; val_offset:12399*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12399*FLEN/8, x13, x9, x10)

inst_4155:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f0007ff; valaddr_reg:x12; val_offset:12402*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12402*FLEN/8, x13, x9, x10)

inst_4156:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7ffc00; valaddr_reg:x12; val_offset:12405*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12405*FLEN/8, x13, x9, x10)

inst_4157:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f0003ff; valaddr_reg:x12; val_offset:12408*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12408*FLEN/8, x13, x9, x10)

inst_4158:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7ffe00; valaddr_reg:x12; val_offset:12411*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12411*FLEN/8, x13, x9, x10)

inst_4159:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f0001ff; valaddr_reg:x12; val_offset:12414*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12414*FLEN/8, x13, x9, x10)

inst_4160:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7fff00; valaddr_reg:x12; val_offset:12417*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12417*FLEN/8, x13, x9, x10)

inst_4161:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f0000ff; valaddr_reg:x12; val_offset:12420*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12420*FLEN/8, x13, x9, x10)

inst_4162:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7fff80; valaddr_reg:x12; val_offset:12423*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12423*FLEN/8, x13, x9, x10)

inst_4163:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f00007f; valaddr_reg:x12; val_offset:12426*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12426*FLEN/8, x13, x9, x10)

inst_4164:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7fffc0; valaddr_reg:x12; val_offset:12429*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12429*FLEN/8, x13, x9, x10)

inst_4165:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f00003f; valaddr_reg:x12; val_offset:12432*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12432*FLEN/8, x13, x9, x10)

inst_4166:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7fffe0; valaddr_reg:x12; val_offset:12435*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12435*FLEN/8, x13, x9, x10)

inst_4167:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f00001f; valaddr_reg:x12; val_offset:12438*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12438*FLEN/8, x13, x9, x10)

inst_4168:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7ffff0; valaddr_reg:x12; val_offset:12441*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12441*FLEN/8, x13, x9, x10)

inst_4169:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f00000f; valaddr_reg:x12; val_offset:12444*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12444*FLEN/8, x13, x9, x10)

inst_4170:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7ffff8; valaddr_reg:x12; val_offset:12447*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12447*FLEN/8, x13, x9, x10)

inst_4171:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f000007; valaddr_reg:x12; val_offset:12450*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12450*FLEN/8, x13, x9, x10)

inst_4172:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7ffffc; valaddr_reg:x12; val_offset:12453*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12453*FLEN/8, x13, x9, x10)

inst_4173:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f000003; valaddr_reg:x12; val_offset:12456*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12456*FLEN/8, x13, x9, x10)

inst_4174:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f7ffffe; valaddr_reg:x12; val_offset:12459*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12459*FLEN/8, x13, x9, x10)

inst_4175:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8f000001; valaddr_reg:x12; val_offset:12462*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12462*FLEN/8, x13, x9, x10)

inst_4176:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x12; val_offset:12465*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12465*FLEN/8, x13, x9, x10)

inst_4177:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x12; val_offset:12468*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12468*FLEN/8, x13, x9, x10)

inst_4178:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x12; val_offset:12471*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12471*FLEN/8, x13, x9, x10)

inst_4179:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x12; val_offset:12474*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12474*FLEN/8, x13, x9, x10)

inst_4180:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12477*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12477*FLEN/8, x13, x9, x10)

inst_4181:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:12480*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12480*FLEN/8, x13, x9, x10)

inst_4182:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x12; val_offset:12483*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12483*FLEN/8, x13, x9, x10)

inst_4183:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x12; val_offset:12486*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12486*FLEN/8, x13, x9, x10)

inst_4184:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x12; val_offset:12489*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12489*FLEN/8, x13, x9, x10)

inst_4185:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x12; val_offset:12492*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12492*FLEN/8, x13, x9, x10)

inst_4186:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x12; val_offset:12495*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12495*FLEN/8, x13, x9, x10)

inst_4187:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x12; val_offset:12498*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12498*FLEN/8, x13, x9, x10)

inst_4188:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x12; val_offset:12501*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12501*FLEN/8, x13, x9, x10)

inst_4189:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x12; val_offset:12504*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12504*FLEN/8, x13, x9, x10)

inst_4190:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x12; val_offset:12507*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12507*FLEN/8, x13, x9, x10)

inst_4191:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21454b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21454b; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x12; val_offset:12510*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12510*FLEN/8, x13, x9, x10)

inst_4192:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f800000; valaddr_reg:x12; val_offset:12513*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12513*FLEN/8, x13, x9, x10)

inst_4193:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fffffff; valaddr_reg:x12; val_offset:12516*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12516*FLEN/8, x13, x9, x10)

inst_4194:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fc00000; valaddr_reg:x12; val_offset:12519*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12519*FLEN/8, x13, x9, x10)

inst_4195:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fbfffff; valaddr_reg:x12; val_offset:12522*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12522*FLEN/8, x13, x9, x10)

inst_4196:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fe00000; valaddr_reg:x12; val_offset:12525*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12525*FLEN/8, x13, x9, x10)

inst_4197:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f9fffff; valaddr_reg:x12; val_offset:12528*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12528*FLEN/8, x13, x9, x10)

inst_4198:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ff00000; valaddr_reg:x12; val_offset:12531*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12531*FLEN/8, x13, x9, x10)

inst_4199:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f8fffff; valaddr_reg:x12; val_offset:12534*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12534*FLEN/8, x13, x9, x10)

inst_4200:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ff80000; valaddr_reg:x12; val_offset:12537*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12537*FLEN/8, x13, x9, x10)

inst_4201:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f87ffff; valaddr_reg:x12; val_offset:12540*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12540*FLEN/8, x13, x9, x10)

inst_4202:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffc0000; valaddr_reg:x12; val_offset:12543*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12543*FLEN/8, x13, x9, x10)

inst_4203:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f83ffff; valaddr_reg:x12; val_offset:12546*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12546*FLEN/8, x13, x9, x10)

inst_4204:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffe0000; valaddr_reg:x12; val_offset:12549*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12549*FLEN/8, x13, x9, x10)

inst_4205:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f81ffff; valaddr_reg:x12; val_offset:12552*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12552*FLEN/8, x13, x9, x10)

inst_4206:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fff0000; valaddr_reg:x12; val_offset:12555*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12555*FLEN/8, x13, x9, x10)

inst_4207:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f80ffff; valaddr_reg:x12; val_offset:12558*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12558*FLEN/8, x13, x9, x10)

inst_4208:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fff8000; valaddr_reg:x12; val_offset:12561*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12561*FLEN/8, x13, x9, x10)

inst_4209:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f807fff; valaddr_reg:x12; val_offset:12564*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12564*FLEN/8, x13, x9, x10)

inst_4210:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fffc000; valaddr_reg:x12; val_offset:12567*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12567*FLEN/8, x13, x9, x10)

inst_4211:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f803fff; valaddr_reg:x12; val_offset:12570*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12570*FLEN/8, x13, x9, x10)

inst_4212:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fffe000; valaddr_reg:x12; val_offset:12573*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12573*FLEN/8, x13, x9, x10)

inst_4213:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f801fff; valaddr_reg:x12; val_offset:12576*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12576*FLEN/8, x13, x9, x10)

inst_4214:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffff000; valaddr_reg:x12; val_offset:12579*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12579*FLEN/8, x13, x9, x10)

inst_4215:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f800fff; valaddr_reg:x12; val_offset:12582*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12582*FLEN/8, x13, x9, x10)

inst_4216:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffff800; valaddr_reg:x12; val_offset:12585*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12585*FLEN/8, x13, x9, x10)

inst_4217:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f8007ff; valaddr_reg:x12; val_offset:12588*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12588*FLEN/8, x13, x9, x10)

inst_4218:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffffc00; valaddr_reg:x12; val_offset:12591*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12591*FLEN/8, x13, x9, x10)

inst_4219:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f8003ff; valaddr_reg:x12; val_offset:12594*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12594*FLEN/8, x13, x9, x10)

inst_4220:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffffe00; valaddr_reg:x12; val_offset:12597*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12597*FLEN/8, x13, x9, x10)

inst_4221:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f8001ff; valaddr_reg:x12; val_offset:12600*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12600*FLEN/8, x13, x9, x10)

inst_4222:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fffff00; valaddr_reg:x12; val_offset:12603*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12603*FLEN/8, x13, x9, x10)

inst_4223:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f8000ff; valaddr_reg:x12; val_offset:12606*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12606*FLEN/8, x13, x9, x10)

inst_4224:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fffff80; valaddr_reg:x12; val_offset:12609*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12609*FLEN/8, x13, x9, x10)

inst_4225:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f80007f; valaddr_reg:x12; val_offset:12612*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12612*FLEN/8, x13, x9, x10)

inst_4226:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fffffc0; valaddr_reg:x12; val_offset:12615*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12615*FLEN/8, x13, x9, x10)

inst_4227:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f80003f; valaddr_reg:x12; val_offset:12618*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12618*FLEN/8, x13, x9, x10)

inst_4228:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fffffe0; valaddr_reg:x12; val_offset:12621*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12621*FLEN/8, x13, x9, x10)

inst_4229:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f80001f; valaddr_reg:x12; val_offset:12624*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12624*FLEN/8, x13, x9, x10)

inst_4230:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffffff0; valaddr_reg:x12; val_offset:12627*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12627*FLEN/8, x13, x9, x10)

inst_4231:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f80000f; valaddr_reg:x12; val_offset:12630*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12630*FLEN/8, x13, x9, x10)

inst_4232:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffffff8; valaddr_reg:x12; val_offset:12633*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12633*FLEN/8, x13, x9, x10)

inst_4233:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f800007; valaddr_reg:x12; val_offset:12636*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12636*FLEN/8, x13, x9, x10)

inst_4234:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffffffc; valaddr_reg:x12; val_offset:12639*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12639*FLEN/8, x13, x9, x10)

inst_4235:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f800003; valaddr_reg:x12; val_offset:12642*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12642*FLEN/8, x13, x9, x10)

inst_4236:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffffffe; valaddr_reg:x12; val_offset:12645*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12645*FLEN/8, x13, x9, x10)

inst_4237:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f800001; valaddr_reg:x12; val_offset:12648*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12648*FLEN/8, x13, x9, x10)

inst_4238:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x12; val_offset:12651*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12651*FLEN/8, x13, x9, x10)

inst_4239:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x12; val_offset:12654*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12654*FLEN/8, x13, x9, x10)

inst_4240:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x12; val_offset:12657*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12657*FLEN/8, x13, x9, x10)

inst_4241:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x12; val_offset:12660*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12660*FLEN/8, x13, x9, x10)

inst_4242:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12663*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12663*FLEN/8, x13, x9, x10)

inst_4243:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:12666*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12666*FLEN/8, x13, x9, x10)

inst_4244:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x12; val_offset:12669*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12669*FLEN/8, x13, x9, x10)

inst_4245:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x12; val_offset:12672*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12672*FLEN/8, x13, x9, x10)

inst_4246:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x12; val_offset:12675*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12675*FLEN/8, x13, x9, x10)

inst_4247:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x12; val_offset:12678*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12678*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_33)
inst_4248:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x12; val_offset:12681*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12681*FLEN/8, x13, x9, x10)

inst_4249:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x12; val_offset:12684*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12684*FLEN/8, x13, x9, x10)

inst_4250:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x12; val_offset:12687*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12687*FLEN/8, x13, x9, x10)

inst_4251:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x12; val_offset:12690*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12690*FLEN/8, x13, x9, x10)

inst_4252:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x12; val_offset:12693*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12693*FLEN/8, x13, x9, x10)

inst_4253:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x12; val_offset:12696*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12696*FLEN/8, x13, x9, x10)

inst_4254:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x90000000; valaddr_reg:x12; val_offset:12699*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12699*FLEN/8, x13, x9, x10)

inst_4255:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907fffff; valaddr_reg:x12; val_offset:12702*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12702*FLEN/8, x13, x9, x10)

inst_4256:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x90400000; valaddr_reg:x12; val_offset:12705*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12705*FLEN/8, x13, x9, x10)

inst_4257:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x903fffff; valaddr_reg:x12; val_offset:12708*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12708*FLEN/8, x13, x9, x10)

inst_4258:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x90600000; valaddr_reg:x12; val_offset:12711*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12711*FLEN/8, x13, x9, x10)

inst_4259:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x901fffff; valaddr_reg:x12; val_offset:12714*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12714*FLEN/8, x13, x9, x10)

inst_4260:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x90700000; valaddr_reg:x12; val_offset:12717*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12717*FLEN/8, x13, x9, x10)

inst_4261:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x900fffff; valaddr_reg:x12; val_offset:12720*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12720*FLEN/8, x13, x9, x10)

inst_4262:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x90780000; valaddr_reg:x12; val_offset:12723*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12723*FLEN/8, x13, x9, x10)

inst_4263:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x9007ffff; valaddr_reg:x12; val_offset:12726*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12726*FLEN/8, x13, x9, x10)

inst_4264:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907c0000; valaddr_reg:x12; val_offset:12729*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12729*FLEN/8, x13, x9, x10)

inst_4265:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x9003ffff; valaddr_reg:x12; val_offset:12732*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12732*FLEN/8, x13, x9, x10)

inst_4266:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907e0000; valaddr_reg:x12; val_offset:12735*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12735*FLEN/8, x13, x9, x10)

inst_4267:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x9001ffff; valaddr_reg:x12; val_offset:12738*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12738*FLEN/8, x13, x9, x10)

inst_4268:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907f0000; valaddr_reg:x12; val_offset:12741*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12741*FLEN/8, x13, x9, x10)

inst_4269:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x9000ffff; valaddr_reg:x12; val_offset:12744*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12744*FLEN/8, x13, x9, x10)

inst_4270:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907f8000; valaddr_reg:x12; val_offset:12747*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12747*FLEN/8, x13, x9, x10)

inst_4271:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x90007fff; valaddr_reg:x12; val_offset:12750*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12750*FLEN/8, x13, x9, x10)

inst_4272:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907fc000; valaddr_reg:x12; val_offset:12753*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12753*FLEN/8, x13, x9, x10)

inst_4273:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x90003fff; valaddr_reg:x12; val_offset:12756*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12756*FLEN/8, x13, x9, x10)

inst_4274:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907fe000; valaddr_reg:x12; val_offset:12759*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12759*FLEN/8, x13, x9, x10)

inst_4275:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x90001fff; valaddr_reg:x12; val_offset:12762*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12762*FLEN/8, x13, x9, x10)

inst_4276:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907ff000; valaddr_reg:x12; val_offset:12765*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12765*FLEN/8, x13, x9, x10)

inst_4277:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x90000fff; valaddr_reg:x12; val_offset:12768*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12768*FLEN/8, x13, x9, x10)

inst_4278:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907ff800; valaddr_reg:x12; val_offset:12771*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12771*FLEN/8, x13, x9, x10)

inst_4279:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x900007ff; valaddr_reg:x12; val_offset:12774*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12774*FLEN/8, x13, x9, x10)

inst_4280:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907ffc00; valaddr_reg:x12; val_offset:12777*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12777*FLEN/8, x13, x9, x10)

inst_4281:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x900003ff; valaddr_reg:x12; val_offset:12780*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12780*FLEN/8, x13, x9, x10)

inst_4282:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907ffe00; valaddr_reg:x12; val_offset:12783*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12783*FLEN/8, x13, x9, x10)

inst_4283:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x900001ff; valaddr_reg:x12; val_offset:12786*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12786*FLEN/8, x13, x9, x10)

inst_4284:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907fff00; valaddr_reg:x12; val_offset:12789*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12789*FLEN/8, x13, x9, x10)

inst_4285:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x900000ff; valaddr_reg:x12; val_offset:12792*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12792*FLEN/8, x13, x9, x10)

inst_4286:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907fff80; valaddr_reg:x12; val_offset:12795*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12795*FLEN/8, x13, x9, x10)

inst_4287:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x9000007f; valaddr_reg:x12; val_offset:12798*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12798*FLEN/8, x13, x9, x10)

inst_4288:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907fffc0; valaddr_reg:x12; val_offset:12801*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12801*FLEN/8, x13, x9, x10)

inst_4289:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x9000003f; valaddr_reg:x12; val_offset:12804*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12804*FLEN/8, x13, x9, x10)

inst_4290:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907fffe0; valaddr_reg:x12; val_offset:12807*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12807*FLEN/8, x13, x9, x10)

inst_4291:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x9000001f; valaddr_reg:x12; val_offset:12810*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12810*FLEN/8, x13, x9, x10)

inst_4292:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907ffff0; valaddr_reg:x12; val_offset:12813*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12813*FLEN/8, x13, x9, x10)

inst_4293:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x9000000f; valaddr_reg:x12; val_offset:12816*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12816*FLEN/8, x13, x9, x10)

inst_4294:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907ffff8; valaddr_reg:x12; val_offset:12819*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12819*FLEN/8, x13, x9, x10)

inst_4295:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x90000007; valaddr_reg:x12; val_offset:12822*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12822*FLEN/8, x13, x9, x10)

inst_4296:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907ffffc; valaddr_reg:x12; val_offset:12825*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12825*FLEN/8, x13, x9, x10)

inst_4297:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x90000003; valaddr_reg:x12; val_offset:12828*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12828*FLEN/8, x13, x9, x10)

inst_4298:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x907ffffe; valaddr_reg:x12; val_offset:12831*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12831*FLEN/8, x13, x9, x10)

inst_4299:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x20 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x90000001; valaddr_reg:x12; val_offset:12834*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12834*FLEN/8, x13, x9, x10)

inst_4300:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x12; val_offset:12837*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12837*FLEN/8, x13, x9, x10)

inst_4301:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x12; val_offset:12840*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12840*FLEN/8, x13, x9, x10)

inst_4302:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x12; val_offset:12843*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12843*FLEN/8, x13, x9, x10)

inst_4303:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x12; val_offset:12846*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12846*FLEN/8, x13, x9, x10)

inst_4304:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12849*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12849*FLEN/8, x13, x9, x10)

inst_4305:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:12852*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12852*FLEN/8, x13, x9, x10)

inst_4306:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x12; val_offset:12855*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12855*FLEN/8, x13, x9, x10)

inst_4307:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x12; val_offset:12858*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12858*FLEN/8, x13, x9, x10)

inst_4308:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x12; val_offset:12861*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12861*FLEN/8, x13, x9, x10)

inst_4309:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x12; val_offset:12864*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12864*FLEN/8, x13, x9, x10)

inst_4310:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x12; val_offset:12867*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12867*FLEN/8, x13, x9, x10)

inst_4311:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x12; val_offset:12870*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12870*FLEN/8, x13, x9, x10)

inst_4312:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x12; val_offset:12873*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12873*FLEN/8, x13, x9, x10)

inst_4313:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x12; val_offset:12876*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12876*FLEN/8, x13, x9, x10)

inst_4314:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x12; val_offset:12879*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12879*FLEN/8, x13, x9, x10)

inst_4315:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0cb0e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0cb0e7; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x12; val_offset:12882*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12882*FLEN/8, x13, x9, x10)

inst_4316:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf000000; valaddr_reg:x12; val_offset:12885*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12885*FLEN/8, x13, x9, x10)

inst_4317:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7fffff; valaddr_reg:x12; val_offset:12888*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12888*FLEN/8, x13, x9, x10)

inst_4318:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf400000; valaddr_reg:x12; val_offset:12891*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12891*FLEN/8, x13, x9, x10)

inst_4319:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf3fffff; valaddr_reg:x12; val_offset:12894*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12894*FLEN/8, x13, x9, x10)

inst_4320:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf600000; valaddr_reg:x12; val_offset:12897*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12897*FLEN/8, x13, x9, x10)

inst_4321:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf1fffff; valaddr_reg:x12; val_offset:12900*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12900*FLEN/8, x13, x9, x10)

inst_4322:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf700000; valaddr_reg:x12; val_offset:12903*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12903*FLEN/8, x13, x9, x10)

inst_4323:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf0fffff; valaddr_reg:x12; val_offset:12906*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12906*FLEN/8, x13, x9, x10)

inst_4324:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf780000; valaddr_reg:x12; val_offset:12909*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12909*FLEN/8, x13, x9, x10)

inst_4325:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf07ffff; valaddr_reg:x12; val_offset:12912*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12912*FLEN/8, x13, x9, x10)

inst_4326:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7c0000; valaddr_reg:x12; val_offset:12915*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12915*FLEN/8, x13, x9, x10)

inst_4327:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf03ffff; valaddr_reg:x12; val_offset:12918*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12918*FLEN/8, x13, x9, x10)

inst_4328:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7e0000; valaddr_reg:x12; val_offset:12921*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12921*FLEN/8, x13, x9, x10)

inst_4329:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf01ffff; valaddr_reg:x12; val_offset:12924*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12924*FLEN/8, x13, x9, x10)

inst_4330:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7f0000; valaddr_reg:x12; val_offset:12927*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12927*FLEN/8, x13, x9, x10)

inst_4331:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf00ffff; valaddr_reg:x12; val_offset:12930*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12930*FLEN/8, x13, x9, x10)

inst_4332:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7f8000; valaddr_reg:x12; val_offset:12933*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12933*FLEN/8, x13, x9, x10)

inst_4333:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf007fff; valaddr_reg:x12; val_offset:12936*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12936*FLEN/8, x13, x9, x10)

inst_4334:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7fc000; valaddr_reg:x12; val_offset:12939*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12939*FLEN/8, x13, x9, x10)

inst_4335:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf003fff; valaddr_reg:x12; val_offset:12942*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12942*FLEN/8, x13, x9, x10)

inst_4336:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7fe000; valaddr_reg:x12; val_offset:12945*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12945*FLEN/8, x13, x9, x10)

inst_4337:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf001fff; valaddr_reg:x12; val_offset:12948*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12948*FLEN/8, x13, x9, x10)

inst_4338:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7ff000; valaddr_reg:x12; val_offset:12951*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12951*FLEN/8, x13, x9, x10)

inst_4339:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf000fff; valaddr_reg:x12; val_offset:12954*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12954*FLEN/8, x13, x9, x10)

inst_4340:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7ff800; valaddr_reg:x12; val_offset:12957*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12957*FLEN/8, x13, x9, x10)

inst_4341:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf0007ff; valaddr_reg:x12; val_offset:12960*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12960*FLEN/8, x13, x9, x10)

inst_4342:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7ffc00; valaddr_reg:x12; val_offset:12963*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12963*FLEN/8, x13, x9, x10)

inst_4343:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf0003ff; valaddr_reg:x12; val_offset:12966*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12966*FLEN/8, x13, x9, x10)

inst_4344:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7ffe00; valaddr_reg:x12; val_offset:12969*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12969*FLEN/8, x13, x9, x10)

inst_4345:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf0001ff; valaddr_reg:x12; val_offset:12972*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12972*FLEN/8, x13, x9, x10)

inst_4346:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7fff00; valaddr_reg:x12; val_offset:12975*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12975*FLEN/8, x13, x9, x10)

inst_4347:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf0000ff; valaddr_reg:x12; val_offset:12978*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12978*FLEN/8, x13, x9, x10)

inst_4348:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7fff80; valaddr_reg:x12; val_offset:12981*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12981*FLEN/8, x13, x9, x10)

inst_4349:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf00007f; valaddr_reg:x12; val_offset:12984*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12984*FLEN/8, x13, x9, x10)

inst_4350:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7fffc0; valaddr_reg:x12; val_offset:12987*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12987*FLEN/8, x13, x9, x10)

inst_4351:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf00003f; valaddr_reg:x12; val_offset:12990*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12990*FLEN/8, x13, x9, x10)

inst_4352:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7fffe0; valaddr_reg:x12; val_offset:12993*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12993*FLEN/8, x13, x9, x10)

inst_4353:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf00001f; valaddr_reg:x12; val_offset:12996*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12996*FLEN/8, x13, x9, x10)

inst_4354:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7ffff0; valaddr_reg:x12; val_offset:12999*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12999*FLEN/8, x13, x9, x10)

inst_4355:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf00000f; valaddr_reg:x12; val_offset:13002*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13002*FLEN/8, x13, x9, x10)

inst_4356:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7ffff8; valaddr_reg:x12; val_offset:13005*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13005*FLEN/8, x13, x9, x10)

inst_4357:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf000007; valaddr_reg:x12; val_offset:13008*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13008*FLEN/8, x13, x9, x10)

inst_4358:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7ffffc; valaddr_reg:x12; val_offset:13011*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13011*FLEN/8, x13, x9, x10)

inst_4359:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf000003; valaddr_reg:x12; val_offset:13014*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13014*FLEN/8, x13, x9, x10)

inst_4360:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf7ffffe; valaddr_reg:x12; val_offset:13017*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13017*FLEN/8, x13, x9, x10)

inst_4361:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0xf000001; valaddr_reg:x12; val_offset:13020*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13020*FLEN/8, x13, x9, x10)

inst_4362:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0x3ffffff8; valaddr_reg:x12; val_offset:13023*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13023*FLEN/8, x13, x9, x10)

inst_4363:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0x3f800007; valaddr_reg:x12; val_offset:13026*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13026*FLEN/8, x13, x9, x10)

inst_4364:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0x3ffffffc; valaddr_reg:x12; val_offset:13029*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13029*FLEN/8, x13, x9, x10)

inst_4365:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0x3f800003; valaddr_reg:x12; val_offset:13032*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13032*FLEN/8, x13, x9, x10)

inst_4366:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0x3ffffffe; valaddr_reg:x12; val_offset:13035*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13035*FLEN/8, x13, x9, x10)

inst_4367:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0x3f800001; valaddr_reg:x12; val_offset:13038*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13038*FLEN/8, x13, x9, x10)

inst_4368:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0x3fb6db6d; valaddr_reg:x12; val_offset:13041*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13041*FLEN/8, x13, x9, x10)

inst_4369:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0x3fedb6db; valaddr_reg:x12; val_offset:13044*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13044*FLEN/8, x13, x9, x10)

inst_4370:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0x3f999999; valaddr_reg:x12; val_offset:13047*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13047*FLEN/8, x13, x9, x10)

inst_4371:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0x3fe66666; valaddr_reg:x12; val_offset:13050*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13050*FLEN/8, x13, x9, x10)

inst_4372:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0x3fbbbbbb; valaddr_reg:x12; val_offset:13053*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13053*FLEN/8, x13, x9, x10)

inst_4373:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0x3fc44444; valaddr_reg:x12; val_offset:13056*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13056*FLEN/8, x13, x9, x10)

inst_4374:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0x3fa49249; valaddr_reg:x12; val_offset:13059*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13059*FLEN/8, x13, x9, x10)

inst_4375:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0x3fdb6db6; valaddr_reg:x12; val_offset:13062*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13062*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_34)
inst_4376:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0x3fb33333; valaddr_reg:x12; val_offset:13065*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13065*FLEN/8, x13, x9, x10)

inst_4377:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0x03 and fm2 == 0x75484b and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d0597cb; op2val:0x1f5484b;
op3val:0x3fcccccc; valaddr_reg:x12; val_offset:13068*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13068*FLEN/8, x13, x9, x10)

inst_4378:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d000000; valaddr_reg:x12; val_offset:13071*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13071*FLEN/8, x13, x9, x10)

inst_4379:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7fffff; valaddr_reg:x12; val_offset:13074*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13074*FLEN/8, x13, x9, x10)

inst_4380:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d400000; valaddr_reg:x12; val_offset:13077*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13077*FLEN/8, x13, x9, x10)

inst_4381:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d3fffff; valaddr_reg:x12; val_offset:13080*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13080*FLEN/8, x13, x9, x10)

inst_4382:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d600000; valaddr_reg:x12; val_offset:13083*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13083*FLEN/8, x13, x9, x10)

inst_4383:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d1fffff; valaddr_reg:x12; val_offset:13086*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13086*FLEN/8, x13, x9, x10)

inst_4384:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d700000; valaddr_reg:x12; val_offset:13089*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13089*FLEN/8, x13, x9, x10)

inst_4385:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d0fffff; valaddr_reg:x12; val_offset:13092*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13092*FLEN/8, x13, x9, x10)

inst_4386:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d780000; valaddr_reg:x12; val_offset:13095*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13095*FLEN/8, x13, x9, x10)

inst_4387:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d07ffff; valaddr_reg:x12; val_offset:13098*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13098*FLEN/8, x13, x9, x10)

inst_4388:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7c0000; valaddr_reg:x12; val_offset:13101*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13101*FLEN/8, x13, x9, x10)

inst_4389:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d03ffff; valaddr_reg:x12; val_offset:13104*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13104*FLEN/8, x13, x9, x10)

inst_4390:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7e0000; valaddr_reg:x12; val_offset:13107*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13107*FLEN/8, x13, x9, x10)

inst_4391:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d01ffff; valaddr_reg:x12; val_offset:13110*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13110*FLEN/8, x13, x9, x10)

inst_4392:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7f0000; valaddr_reg:x12; val_offset:13113*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13113*FLEN/8, x13, x9, x10)

inst_4393:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d00ffff; valaddr_reg:x12; val_offset:13116*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13116*FLEN/8, x13, x9, x10)

inst_4394:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7f8000; valaddr_reg:x12; val_offset:13119*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13119*FLEN/8, x13, x9, x10)

inst_4395:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d007fff; valaddr_reg:x12; val_offset:13122*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13122*FLEN/8, x13, x9, x10)

inst_4396:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7fc000; valaddr_reg:x12; val_offset:13125*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13125*FLEN/8, x13, x9, x10)

inst_4397:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d003fff; valaddr_reg:x12; val_offset:13128*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13128*FLEN/8, x13, x9, x10)

inst_4398:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7fe000; valaddr_reg:x12; val_offset:13131*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13131*FLEN/8, x13, x9, x10)

inst_4399:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d001fff; valaddr_reg:x12; val_offset:13134*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13134*FLEN/8, x13, x9, x10)

inst_4400:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7ff000; valaddr_reg:x12; val_offset:13137*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13137*FLEN/8, x13, x9, x10)

inst_4401:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d000fff; valaddr_reg:x12; val_offset:13140*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13140*FLEN/8, x13, x9, x10)

inst_4402:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7ff800; valaddr_reg:x12; val_offset:13143*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13143*FLEN/8, x13, x9, x10)

inst_4403:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d0007ff; valaddr_reg:x12; val_offset:13146*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13146*FLEN/8, x13, x9, x10)

inst_4404:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7ffc00; valaddr_reg:x12; val_offset:13149*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13149*FLEN/8, x13, x9, x10)

inst_4405:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d0003ff; valaddr_reg:x12; val_offset:13152*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13152*FLEN/8, x13, x9, x10)

inst_4406:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7ffe00; valaddr_reg:x12; val_offset:13155*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13155*FLEN/8, x13, x9, x10)

inst_4407:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d0001ff; valaddr_reg:x12; val_offset:13158*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13158*FLEN/8, x13, x9, x10)

inst_4408:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7fff00; valaddr_reg:x12; val_offset:13161*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13161*FLEN/8, x13, x9, x10)

inst_4409:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d0000ff; valaddr_reg:x12; val_offset:13164*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13164*FLEN/8, x13, x9, x10)

inst_4410:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7fff80; valaddr_reg:x12; val_offset:13167*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13167*FLEN/8, x13, x9, x10)

inst_4411:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d00007f; valaddr_reg:x12; val_offset:13170*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13170*FLEN/8, x13, x9, x10)

inst_4412:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7fffc0; valaddr_reg:x12; val_offset:13173*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13173*FLEN/8, x13, x9, x10)

inst_4413:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d00003f; valaddr_reg:x12; val_offset:13176*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13176*FLEN/8, x13, x9, x10)

inst_4414:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7fffe0; valaddr_reg:x12; val_offset:13179*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13179*FLEN/8, x13, x9, x10)

inst_4415:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d00001f; valaddr_reg:x12; val_offset:13182*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13182*FLEN/8, x13, x9, x10)

inst_4416:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7ffff0; valaddr_reg:x12; val_offset:13185*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13185*FLEN/8, x13, x9, x10)

inst_4417:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d00000f; valaddr_reg:x12; val_offset:13188*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13188*FLEN/8, x13, x9, x10)

inst_4418:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7ffff8; valaddr_reg:x12; val_offset:13191*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13191*FLEN/8, x13, x9, x10)

inst_4419:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d000007; valaddr_reg:x12; val_offset:13194*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13194*FLEN/8, x13, x9, x10)

inst_4420:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7ffffc; valaddr_reg:x12; val_offset:13197*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13197*FLEN/8, x13, x9, x10)

inst_4421:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d000003; valaddr_reg:x12; val_offset:13200*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13200*FLEN/8, x13, x9, x10)

inst_4422:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d7ffffe; valaddr_reg:x12; val_offset:13203*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13203*FLEN/8, x13, x9, x10)

inst_4423:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0xfa and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x7d000001; valaddr_reg:x12; val_offset:13206*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13206*FLEN/8, x13, x9, x10)

inst_4424:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x3ffffff8; valaddr_reg:x12; val_offset:13209*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13209*FLEN/8, x13, x9, x10)

inst_4425:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x3f800007; valaddr_reg:x12; val_offset:13212*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13212*FLEN/8, x13, x9, x10)

inst_4426:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x3ffffffc; valaddr_reg:x12; val_offset:13215*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13215*FLEN/8, x13, x9, x10)

inst_4427:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x3f800003; valaddr_reg:x12; val_offset:13218*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13218*FLEN/8, x13, x9, x10)

inst_4428:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x3ffffffe; valaddr_reg:x12; val_offset:13221*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13221*FLEN/8, x13, x9, x10)

inst_4429:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x3f800001; valaddr_reg:x12; val_offset:13224*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13224*FLEN/8, x13, x9, x10)

inst_4430:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x3fb6db6d; valaddr_reg:x12; val_offset:13227*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13227*FLEN/8, x13, x9, x10)

inst_4431:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x3fedb6db; valaddr_reg:x12; val_offset:13230*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13230*FLEN/8, x13, x9, x10)

inst_4432:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x3f999999; valaddr_reg:x12; val_offset:13233*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13233*FLEN/8, x13, x9, x10)

inst_4433:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x3fe66666; valaddr_reg:x12; val_offset:13236*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13236*FLEN/8, x13, x9, x10)

inst_4434:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x3fbbbbbb; valaddr_reg:x12; val_offset:13239*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13239*FLEN/8, x13, x9, x10)

inst_4435:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x3fc44444; valaddr_reg:x12; val_offset:13242*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13242*FLEN/8, x13, x9, x10)

inst_4436:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x3fa49249; valaddr_reg:x12; val_offset:13245*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13245*FLEN/8, x13, x9, x10)

inst_4437:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x3fdb6db6; valaddr_reg:x12; val_offset:13248*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13248*FLEN/8, x13, x9, x10)

inst_4438:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x3fb33333; valaddr_reg:x12; val_offset:13251*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13251*FLEN/8, x13, x9, x10)

inst_4439:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22dfb7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x324bec and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f22dfb7; op2val:0x324bec;
op3val:0x3fcccccc; valaddr_reg:x12; val_offset:13254*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13254*FLEN/8, x13, x9, x10)

inst_4440:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f000000; valaddr_reg:x12; val_offset:13257*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13257*FLEN/8, x13, x9, x10)

inst_4441:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7fffff; valaddr_reg:x12; val_offset:13260*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13260*FLEN/8, x13, x9, x10)

inst_4442:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f400000; valaddr_reg:x12; val_offset:13263*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13263*FLEN/8, x13, x9, x10)

inst_4443:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f3fffff; valaddr_reg:x12; val_offset:13266*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13266*FLEN/8, x13, x9, x10)

inst_4444:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f600000; valaddr_reg:x12; val_offset:13269*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13269*FLEN/8, x13, x9, x10)

inst_4445:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f1fffff; valaddr_reg:x12; val_offset:13272*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13272*FLEN/8, x13, x9, x10)

inst_4446:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f700000; valaddr_reg:x12; val_offset:13275*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13275*FLEN/8, x13, x9, x10)

inst_4447:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f0fffff; valaddr_reg:x12; val_offset:13278*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13278*FLEN/8, x13, x9, x10)

inst_4448:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f780000; valaddr_reg:x12; val_offset:13281*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13281*FLEN/8, x13, x9, x10)

inst_4449:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f07ffff; valaddr_reg:x12; val_offset:13284*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13284*FLEN/8, x13, x9, x10)

inst_4450:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7c0000; valaddr_reg:x12; val_offset:13287*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13287*FLEN/8, x13, x9, x10)

inst_4451:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f03ffff; valaddr_reg:x12; val_offset:13290*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13290*FLEN/8, x13, x9, x10)

inst_4452:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7e0000; valaddr_reg:x12; val_offset:13293*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13293*FLEN/8, x13, x9, x10)

inst_4453:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f01ffff; valaddr_reg:x12; val_offset:13296*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13296*FLEN/8, x13, x9, x10)

inst_4454:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7f0000; valaddr_reg:x12; val_offset:13299*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13299*FLEN/8, x13, x9, x10)

inst_4455:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f00ffff; valaddr_reg:x12; val_offset:13302*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13302*FLEN/8, x13, x9, x10)

inst_4456:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7f8000; valaddr_reg:x12; val_offset:13305*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13305*FLEN/8, x13, x9, x10)

inst_4457:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f007fff; valaddr_reg:x12; val_offset:13308*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13308*FLEN/8, x13, x9, x10)

inst_4458:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7fc000; valaddr_reg:x12; val_offset:13311*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13311*FLEN/8, x13, x9, x10)

inst_4459:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f003fff; valaddr_reg:x12; val_offset:13314*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13314*FLEN/8, x13, x9, x10)

inst_4460:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7fe000; valaddr_reg:x12; val_offset:13317*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13317*FLEN/8, x13, x9, x10)

inst_4461:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f001fff; valaddr_reg:x12; val_offset:13320*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13320*FLEN/8, x13, x9, x10)

inst_4462:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7ff000; valaddr_reg:x12; val_offset:13323*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13323*FLEN/8, x13, x9, x10)

inst_4463:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f000fff; valaddr_reg:x12; val_offset:13326*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13326*FLEN/8, x13, x9, x10)

inst_4464:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7ff800; valaddr_reg:x12; val_offset:13329*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13329*FLEN/8, x13, x9, x10)

inst_4465:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f0007ff; valaddr_reg:x12; val_offset:13332*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13332*FLEN/8, x13, x9, x10)

inst_4466:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7ffc00; valaddr_reg:x12; val_offset:13335*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13335*FLEN/8, x13, x9, x10)

inst_4467:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f0003ff; valaddr_reg:x12; val_offset:13338*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13338*FLEN/8, x13, x9, x10)

inst_4468:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7ffe00; valaddr_reg:x12; val_offset:13341*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13341*FLEN/8, x13, x9, x10)

inst_4469:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f0001ff; valaddr_reg:x12; val_offset:13344*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13344*FLEN/8, x13, x9, x10)

inst_4470:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7fff00; valaddr_reg:x12; val_offset:13347*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13347*FLEN/8, x13, x9, x10)

inst_4471:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f0000ff; valaddr_reg:x12; val_offset:13350*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13350*FLEN/8, x13, x9, x10)

inst_4472:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7fff80; valaddr_reg:x12; val_offset:13353*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13353*FLEN/8, x13, x9, x10)

inst_4473:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f00007f; valaddr_reg:x12; val_offset:13356*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13356*FLEN/8, x13, x9, x10)

inst_4474:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7fffc0; valaddr_reg:x12; val_offset:13359*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13359*FLEN/8, x13, x9, x10)

inst_4475:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f00003f; valaddr_reg:x12; val_offset:13362*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13362*FLEN/8, x13, x9, x10)

inst_4476:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7fffe0; valaddr_reg:x12; val_offset:13365*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13365*FLEN/8, x13, x9, x10)

inst_4477:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f00001f; valaddr_reg:x12; val_offset:13368*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13368*FLEN/8, x13, x9, x10)

inst_4478:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7ffff0; valaddr_reg:x12; val_offset:13371*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13371*FLEN/8, x13, x9, x10)

inst_4479:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f00000f; valaddr_reg:x12; val_offset:13374*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13374*FLEN/8, x13, x9, x10)

inst_4480:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7ffff8; valaddr_reg:x12; val_offset:13377*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13377*FLEN/8, x13, x9, x10)

inst_4481:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f000007; valaddr_reg:x12; val_offset:13380*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13380*FLEN/8, x13, x9, x10)

inst_4482:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7ffffc; valaddr_reg:x12; val_offset:13383*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13383*FLEN/8, x13, x9, x10)

inst_4483:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f000003; valaddr_reg:x12; val_offset:13386*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13386*FLEN/8, x13, x9, x10)

inst_4484:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f7ffffe; valaddr_reg:x12; val_offset:13389*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13389*FLEN/8, x13, x9, x10)

inst_4485:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x3e and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x1f000001; valaddr_reg:x12; val_offset:13392*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13392*FLEN/8, x13, x9, x10)

inst_4486:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x3ffffff8; valaddr_reg:x12; val_offset:13395*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13395*FLEN/8, x13, x9, x10)

inst_4487:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x3f800007; valaddr_reg:x12; val_offset:13398*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13398*FLEN/8, x13, x9, x10)

inst_4488:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x3ffffffc; valaddr_reg:x12; val_offset:13401*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13401*FLEN/8, x13, x9, x10)

inst_4489:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x3f800003; valaddr_reg:x12; val_offset:13404*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13404*FLEN/8, x13, x9, x10)

inst_4490:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x3ffffffe; valaddr_reg:x12; val_offset:13407*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13407*FLEN/8, x13, x9, x10)

inst_4491:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x3f800001; valaddr_reg:x12; val_offset:13410*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13410*FLEN/8, x13, x9, x10)

inst_4492:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x3fb6db6d; valaddr_reg:x12; val_offset:13413*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13413*FLEN/8, x13, x9, x10)

inst_4493:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x3fedb6db; valaddr_reg:x12; val_offset:13416*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13416*FLEN/8, x13, x9, x10)

inst_4494:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x3f999999; valaddr_reg:x12; val_offset:13419*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13419*FLEN/8, x13, x9, x10)

inst_4495:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x3fe66666; valaddr_reg:x12; val_offset:13422*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13422*FLEN/8, x13, x9, x10)

inst_4496:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x3fbbbbbb; valaddr_reg:x12; val_offset:13425*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13425*FLEN/8, x13, x9, x10)

inst_4497:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x3fc44444; valaddr_reg:x12; val_offset:13428*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13428*FLEN/8, x13, x9, x10)

inst_4498:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x3fa49249; valaddr_reg:x12; val_offset:13431*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13431*FLEN/8, x13, x9, x10)

inst_4499:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x3fdb6db6; valaddr_reg:x12; val_offset:13434*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13434*FLEN/8, x13, x9, x10)

inst_4500:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x3fb33333; valaddr_reg:x12; val_offset:13437*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13437*FLEN/8, x13, x9, x10)

inst_4501:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6c1659 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4565e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eec1659; op2val:0x4565e6;
op3val:0x3fcccccc; valaddr_reg:x12; val_offset:13440*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13440*FLEN/8, x13, x9, x10)

inst_4502:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f800000; valaddr_reg:x12; val_offset:13443*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13443*FLEN/8, x13, x9, x10)

inst_4503:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1fffffff; valaddr_reg:x12; val_offset:13446*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13446*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_35)
inst_4504:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1fc00000; valaddr_reg:x12; val_offset:13449*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13449*FLEN/8, x13, x9, x10)

inst_4505:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1fbfffff; valaddr_reg:x12; val_offset:13452*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13452*FLEN/8, x13, x9, x10)

inst_4506:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1fe00000; valaddr_reg:x12; val_offset:13455*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13455*FLEN/8, x13, x9, x10)

inst_4507:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f9fffff; valaddr_reg:x12; val_offset:13458*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13458*FLEN/8, x13, x9, x10)

inst_4508:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1ff00000; valaddr_reg:x12; val_offset:13461*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13461*FLEN/8, x13, x9, x10)

inst_4509:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f8fffff; valaddr_reg:x12; val_offset:13464*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13464*FLEN/8, x13, x9, x10)

inst_4510:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1ff80000; valaddr_reg:x12; val_offset:13467*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13467*FLEN/8, x13, x9, x10)

inst_4511:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f87ffff; valaddr_reg:x12; val_offset:13470*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13470*FLEN/8, x13, x9, x10)

inst_4512:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1ffc0000; valaddr_reg:x12; val_offset:13473*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13473*FLEN/8, x13, x9, x10)

inst_4513:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f83ffff; valaddr_reg:x12; val_offset:13476*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13476*FLEN/8, x13, x9, x10)

inst_4514:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1ffe0000; valaddr_reg:x12; val_offset:13479*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13479*FLEN/8, x13, x9, x10)

inst_4515:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f81ffff; valaddr_reg:x12; val_offset:13482*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13482*FLEN/8, x13, x9, x10)

inst_4516:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1fff0000; valaddr_reg:x12; val_offset:13485*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13485*FLEN/8, x13, x9, x10)

inst_4517:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f80ffff; valaddr_reg:x12; val_offset:13488*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13488*FLEN/8, x13, x9, x10)

inst_4518:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1fff8000; valaddr_reg:x12; val_offset:13491*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13491*FLEN/8, x13, x9, x10)

inst_4519:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f807fff; valaddr_reg:x12; val_offset:13494*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13494*FLEN/8, x13, x9, x10)

inst_4520:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1fffc000; valaddr_reg:x12; val_offset:13497*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13497*FLEN/8, x13, x9, x10)

inst_4521:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f803fff; valaddr_reg:x12; val_offset:13500*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13500*FLEN/8, x13, x9, x10)

inst_4522:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1fffe000; valaddr_reg:x12; val_offset:13503*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13503*FLEN/8, x13, x9, x10)

inst_4523:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f801fff; valaddr_reg:x12; val_offset:13506*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13506*FLEN/8, x13, x9, x10)

inst_4524:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1ffff000; valaddr_reg:x12; val_offset:13509*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13509*FLEN/8, x13, x9, x10)

inst_4525:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f800fff; valaddr_reg:x12; val_offset:13512*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13512*FLEN/8, x13, x9, x10)

inst_4526:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1ffff800; valaddr_reg:x12; val_offset:13515*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13515*FLEN/8, x13, x9, x10)

inst_4527:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f8007ff; valaddr_reg:x12; val_offset:13518*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13518*FLEN/8, x13, x9, x10)

inst_4528:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1ffffc00; valaddr_reg:x12; val_offset:13521*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13521*FLEN/8, x13, x9, x10)

inst_4529:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f8003ff; valaddr_reg:x12; val_offset:13524*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13524*FLEN/8, x13, x9, x10)

inst_4530:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1ffffe00; valaddr_reg:x12; val_offset:13527*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13527*FLEN/8, x13, x9, x10)

inst_4531:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f8001ff; valaddr_reg:x12; val_offset:13530*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13530*FLEN/8, x13, x9, x10)

inst_4532:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1fffff00; valaddr_reg:x12; val_offset:13533*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13533*FLEN/8, x13, x9, x10)

inst_4533:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f8000ff; valaddr_reg:x12; val_offset:13536*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13536*FLEN/8, x13, x9, x10)

inst_4534:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1fffff80; valaddr_reg:x12; val_offset:13539*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13539*FLEN/8, x13, x9, x10)

inst_4535:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f80007f; valaddr_reg:x12; val_offset:13542*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13542*FLEN/8, x13, x9, x10)

inst_4536:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1fffffc0; valaddr_reg:x12; val_offset:13545*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13545*FLEN/8, x13, x9, x10)

inst_4537:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f80003f; valaddr_reg:x12; val_offset:13548*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13548*FLEN/8, x13, x9, x10)

inst_4538:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1fffffe0; valaddr_reg:x12; val_offset:13551*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13551*FLEN/8, x13, x9, x10)

inst_4539:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f80001f; valaddr_reg:x12; val_offset:13554*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13554*FLEN/8, x13, x9, x10)

inst_4540:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1ffffff0; valaddr_reg:x12; val_offset:13557*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13557*FLEN/8, x13, x9, x10)

inst_4541:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f80000f; valaddr_reg:x12; val_offset:13560*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13560*FLEN/8, x13, x9, x10)

inst_4542:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1ffffff8; valaddr_reg:x12; val_offset:13563*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13563*FLEN/8, x13, x9, x10)

inst_4543:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f800007; valaddr_reg:x12; val_offset:13566*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13566*FLEN/8, x13, x9, x10)

inst_4544:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1ffffffc; valaddr_reg:x12; val_offset:13569*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13569*FLEN/8, x13, x9, x10)

inst_4545:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f800003; valaddr_reg:x12; val_offset:13572*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13572*FLEN/8, x13, x9, x10)

inst_4546:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1ffffffe; valaddr_reg:x12; val_offset:13575*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13575*FLEN/8, x13, x9, x10)

inst_4547:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x3f and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x1f800001; valaddr_reg:x12; val_offset:13578*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13578*FLEN/8, x13, x9, x10)

inst_4548:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x3ffffff8; valaddr_reg:x12; val_offset:13581*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13581*FLEN/8, x13, x9, x10)

inst_4549:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x3f800007; valaddr_reg:x12; val_offset:13584*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13584*FLEN/8, x13, x9, x10)

inst_4550:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x3ffffffc; valaddr_reg:x12; val_offset:13587*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13587*FLEN/8, x13, x9, x10)

inst_4551:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x3f800003; valaddr_reg:x12; val_offset:13590*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13590*FLEN/8, x13, x9, x10)

inst_4552:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x3ffffffe; valaddr_reg:x12; val_offset:13593*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13593*FLEN/8, x13, x9, x10)

inst_4553:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x3f800001; valaddr_reg:x12; val_offset:13596*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13596*FLEN/8, x13, x9, x10)

inst_4554:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x3fb6db6d; valaddr_reg:x12; val_offset:13599*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13599*FLEN/8, x13, x9, x10)

inst_4555:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x3fedb6db; valaddr_reg:x12; val_offset:13602*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13602*FLEN/8, x13, x9, x10)

inst_4556:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x3f999999; valaddr_reg:x12; val_offset:13605*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13605*FLEN/8, x13, x9, x10)

inst_4557:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x3fe66666; valaddr_reg:x12; val_offset:13608*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13608*FLEN/8, x13, x9, x10)

inst_4558:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x3fbbbbbb; valaddr_reg:x12; val_offset:13611*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13611*FLEN/8, x13, x9, x10)

inst_4559:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x3fc44444; valaddr_reg:x12; val_offset:13614*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13614*FLEN/8, x13, x9, x10)

inst_4560:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e0500 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x49cb99 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede0500; op2val:0x49cb99;
op3val:0x3fa49249; valaddr_reg:x12; val_offset:13617*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13617*FLEN/8, x13, x9, x10)

#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365571072,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2357215231,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365579264,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2357207039,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365583360,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2357202943,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365585408,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2357200895,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365586432,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2357199871,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365586944,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2357199359,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365587200,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2357199103,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365587328,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2357198975,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365587392,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2357198911,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365587424,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2357198879,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365587440,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2357198863,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365587448,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2357198855,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365587452,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2357198851,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365587454,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2357198849,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872248,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483655,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872252,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483651,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151078765,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154673883,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149161369,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154194534,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151398331,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151957572,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149880393,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2153475510,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2150839091,32,FLEN)
NAN_BOXED(2131606723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2152516812,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365587456,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373976063,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2369781760,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2369781759,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2371878912,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2367684607,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2372927488,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2366636031,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373451776,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2366111743,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373713920,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365849599,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373844992,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365718527,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373910528,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365652991,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373943296,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365620223,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373959680,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365603839,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373967872,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365595647,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373971968,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365591551,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373974016,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365589503,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373975040,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365588479,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373975552,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365587967,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373975808,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365587711,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373975936,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365587583,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373976000,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365587519,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373976032,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365587487,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373976048,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365587471,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373976056,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365587463,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373976060,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365587459,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373976062,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2365587457,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872248,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483655,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872252,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483651,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151078765,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154673883,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149161369,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154194534,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151398331,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151957572,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149880393,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2153475510,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2150839091,32,FLEN)
NAN_BOXED(2105856112,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2152516812,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373976064,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364671,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2378170368,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2378170367,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2380267520,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2376073215,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2381316096,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2375024639,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2381840384,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2374500351,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382102528,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2374238207,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382233600,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2374107135,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382299136,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2374041599,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382331904,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2374008831,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382348288,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373992447,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382356480,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373984255,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382360576,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373980159,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382362624,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373978111,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382363648,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373977087,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364160,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373976575,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364416,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373976319,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364544,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373976191,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364608,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373976127,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364640,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373976095,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364656,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373976079,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364664,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373976071,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364668,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373976067,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364670,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2373976065,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872248,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483655,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872252,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483651,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151078765,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154673883,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149161369,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154194534,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151398331,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151957572,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149880393,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2153475510,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2150839091,32,FLEN)
NAN_BOXED(2130633227,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2152516812,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364672,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753279,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2386558976,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2386558975,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2388656128,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2384461823,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2389704704,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2383413247,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390228992,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382888959,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390491136,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382626815,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390622208,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382495743,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390687744,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382430207,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390720512,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382397439,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390736896,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382381055,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390745088,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382372863,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390749184,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382368767,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390751232,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382366719,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390752256,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382365695,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390752768,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382365183,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753024,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364927,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753152,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364799,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753216,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364735,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753248,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364703,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753264,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364687,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753272,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364679,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753276,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364675,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753278,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2382364673,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872248,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483655,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872252,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483651,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151078765,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154673883,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149161369,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154194534,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151398331,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151957572,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149880393,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2153475510,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2150839091,32,FLEN)
NAN_BOXED(2108016716,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2152516812,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753280,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399141887,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2394947584,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2394947583,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2397044736,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2392850431,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2398093312,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2391801855,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2398617600,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2391277567,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2398879744,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2391015423,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399010816,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390884351,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399076352,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390818815,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399109120,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390786047,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399125504,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390769663,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399133696,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390761471,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399137792,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390757375,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399139840,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390755327,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399140864,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390754303,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399141376,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753791,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399141632,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753535,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399141760,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753407,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399141824,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753343,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399141856,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753311,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399141872,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753295,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399141880,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753287,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399141884,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753283,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399141886,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2390753281,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872248,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483655,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872252,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483651,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151078765,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154673883,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149161369,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154194534,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151398331,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151957572,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149880393,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2153475510,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2150839091,32,FLEN)
NAN_BOXED(2113630409,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2152516812,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399141888,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407530495,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2403336192,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2403336191,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2405433344,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2401239039,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2406481920,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2400190463,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407006208,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399666175,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407268352,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399404031,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407399424,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399272959,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407464960,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399207423,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407497728,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399174655,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407514112,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399158271,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407522304,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399150079,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407526400,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399145983,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407528448,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399143935,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407529472,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399142911,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407529984,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399142399,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407530240,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399142143,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407530368,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399142015,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407530432,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399141951,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407530464,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399141919,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407530480,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399141903,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407530488,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399141895,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407530492,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399141891,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407530494,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2399141889,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872248,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483655,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872252,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483651,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151078765,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154673883,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149161369,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154194534,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151398331,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151957572,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149880393,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2153475510,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2150839091,32,FLEN)
NAN_BOXED(2132886859,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2152516812,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407530496,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415919103,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2411724800,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2411724799,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2413821952,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2409627647,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2414870528,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2408579071,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415394816,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2408054783,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415656960,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407792639,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415788032,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407661567,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415853568,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407596031,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415886336,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407563263,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415902720,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407546879,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415910912,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407538687,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415915008,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407534591,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415917056,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407532543,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415918080,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407531519,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415918592,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407531007,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415918848,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407530751,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415918976,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407530623,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415919040,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407530559,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415919072,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407530527,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415919088,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407530511,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415919096,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407530503,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415919100,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407530499,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415919102,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2407530497,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872248,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483655,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872252,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483651,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151078765,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154673883,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149161369,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154194534,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151398331,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151957572,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149880393,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2153475510,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2150839091,32,FLEN)
NAN_BOXED(2123253723,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2152516812,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415919104,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424307711,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2420113408,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2420113407,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2422210560,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2418016255,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2423259136,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2416967679,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2423783424,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2416443391,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424045568,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2416181247,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424176640,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2416050175,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424242176,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415984639,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424274944,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415951871,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424291328,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415935487,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424299520,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415927295,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424303616,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415923199,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424305664,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415921151,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424306688,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415920127,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424307200,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415919615,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424307456,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415919359,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424307584,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415919231,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424307648,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415919167,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424307680,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415919135,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424307696,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415919119,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424307704,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415919111,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424307708,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415919107,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2424307710,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2415919105,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872248,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483655,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872252,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483651,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151078765,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154673883,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149161369,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2154194534,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151398331,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2151957572,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2149880393,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2153475510,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2150839091,32,FLEN)
NAN_BOXED(2131538151,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2152516812,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251658240,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(260046847,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(255852544,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(255852543,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(257949696,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(253755391,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(258998272,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(252706815,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(259522560,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(252182527,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(259784704,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251920383,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(259915776,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251789311,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(259981312,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251723775,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(260014080,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251691007,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(260030464,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251674623,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(260038656,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251666431,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(260042752,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251662335,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(260044800,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251660287,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(260045824,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251659263,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(260046336,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251658751,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(260046592,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251658495,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(260046720,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251658367,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(260046784,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251658303,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(260046816,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251658271,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(260046832,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251658255,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(260046840,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251658247,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(260046844,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251658243,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(260046846,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(251658241,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(1073741816,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(1065353223,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(1073741820,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(1065353219,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(1073741822,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(1065353217,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(1068948333,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(1072543451,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(1067030937,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(1072064102,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(1069267899,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(1069827140,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(1067749961,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(1071345078,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(1068708659,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(32852043,32,FLEN)
NAN_BOXED(1070386380,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097152000,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105540607,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2101346304,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2101346303,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2103443456,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2099249151,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2104492032,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2098200575,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105016320,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097676287,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105278464,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097414143,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105409536,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097283071,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105475072,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097217535,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105507840,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097184767,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105524224,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097168383,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105532416,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097160191,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105536512,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097156095,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105538560,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097154047,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105539584,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097153023,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105540096,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097152511,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105540352,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097152255,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105540480,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097152127,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105540544,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097152063,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105540576,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097152031,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105540592,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097152015,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105540600,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097152007,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105540604,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097152003,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2105540606,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(2097152001,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(1073741816,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(1065353223,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(1073741820,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(1065353219,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(1073741822,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(1065353217,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(1068948333,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(1072543451,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(1067030937,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(1072064102,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(1069267899,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(1069827140,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(1067749961,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(1071345078,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(1068708659,32,FLEN)
NAN_BOXED(2132991927,32,FLEN)
NAN_BOXED(3296236,32,FLEN)
NAN_BOXED(1070386380,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520093696,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528482303,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(524288000,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(524287999,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(526385152,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(522190847,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(527433728,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(521142271,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(527958016,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520617983,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528220160,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520355839,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528351232,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520224767,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528416768,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520159231,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528449536,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520126463,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528465920,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520110079,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528474112,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520101887,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528478208,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520097791,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528480256,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520095743,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528481280,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520094719,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528481792,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520094207,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528482048,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520093951,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528482176,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520093823,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528482240,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520093759,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528482272,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520093727,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528482288,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520093711,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528482296,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520093703,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528482300,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520093699,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(528482302,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(520093697,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(1073741816,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(1065353223,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(1073741820,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(1065353219,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(1073741822,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(1065353217,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(1068948333,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(1072543451,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(1067030937,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(1072064102,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(1069267899,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(1069827140,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(1067749961,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(1071345078,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(1068708659,32,FLEN)
NAN_BOXED(2129401433,32,FLEN)
NAN_BOXED(4548070,32,FLEN)
NAN_BOXED(1070386380,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528482304,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536870911,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(532676608,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(532676607,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(534773760,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(530579455,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(535822336,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(529530879,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536346624,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(529006591,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536608768,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528744447,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536739840,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528613375,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536805376,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528547839,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536838144,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528515071,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536854528,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528498687,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536862720,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528490495,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536866816,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528486399,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536868864,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528484351,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536869888,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528483327,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536870400,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528482815,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536870656,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528482559,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536870784,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528482431,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536870848,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528482367,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536870880,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528482335,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536870896,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528482319,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536870904,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528482311,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536870908,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528482307,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(536870910,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(528482305,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(1073741816,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(1065353223,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(1073741820,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(1065353219,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(1073741822,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(1065353217,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(1068948333,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(1072543451,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(1067030937,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(1072064102,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(1069267899,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(1069827140,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(1067749961,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(1071345078,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(1068708659,32,FLEN)
NAN_BOXED(2128479488,32,FLEN)
NAN_BOXED(4836249,32,FLEN)
NAN_BOXED(1070386380,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(536870912,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(545259519,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(541065216,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(541065215,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(543162368,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(538968063,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(544210944,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(537919487,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(544735232,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(537395199,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(544997376,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(537133055,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(545128448,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(537001983,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(545193984,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(536936447,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(545226752,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(536903679,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(545243136,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(536887295,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(545251328,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(536879103,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(545255424,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(536875007,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(545257472,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(536872959,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(545258496,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(536871935,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(545259008,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(536871423,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(545259264,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(536871167,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(545259392,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(536871039,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(545259456,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(536870975,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(545259488,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(536870943,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(545259504,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(536870927,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(545259512,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
NAN_BOXED(4320754,32,FLEN)
NAN_BOXED(536870919,32,FLEN)
NAN_BOXED(2130215433,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 48*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_0:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_7:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_8:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_9:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_10:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_11:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_12:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_13:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_14:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_15:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_16:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_17:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_18:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_19:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_20:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_21:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_22:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_23:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_24:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_25:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_26:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_27:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_28:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_29:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_30:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_31:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_32:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_33:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_34:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_35:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_36:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_37:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_38:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_39:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_40:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_41:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_42:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_43:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_44:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_45:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_46:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_47:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_48:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_49:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_50:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_51:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_52:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_53:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_54:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_55:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_56:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_57:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_58:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_59:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_60:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_61:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_62:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_63:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_64:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_65:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_66:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_67:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_68:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_69:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_70:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_71:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_72:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_73:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_74:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_75:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_76:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_77:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_78:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_79:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_80:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_81:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_82:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_83:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_84:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_85:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_86:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_87:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_88:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_89:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_90:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_91:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_92:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_93:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_94:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_95:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_96:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_97:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_98:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_99:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_100:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_101:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_102:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_103:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_104:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_105:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_106:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_107:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_108:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_109:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_110:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_111:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_112:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_113:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_114:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_115:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_116:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_117:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_118:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_119:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_120:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_121:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_122:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_123:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_124:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_125:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_126:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_127:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_128:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_129:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_130:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_131:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_132:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_133:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_134:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_135:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_136:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_137:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_138:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_139:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_140:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_141:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_142:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_143:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_144:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_145:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_146:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_147:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_148:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_149:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_150:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_151:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_152:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_153:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_154:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_155:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_156:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_157:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_158:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_159:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_160:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_161:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_162:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_163:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_164:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_165:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_166:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_167:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_168:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_169:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_170:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_171:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_172:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_173:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_174:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_175:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_176:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_177:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_178:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_179:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_180:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_181:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_182:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_183:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_184:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_185:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_186:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_187:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_188:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_189:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_190:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_191:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_192:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_193:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_194:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_195:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_196:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_197:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_198:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_199:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_200:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_201:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_202:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_203:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_204:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_205:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_206:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_207:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_208:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_209:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_210:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_211:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_212:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_213:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_214:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_215:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_216:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_217:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_218:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_219:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_220:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_221:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_222:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_223:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_224:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_225:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_226:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_227:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_228:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_229:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_230:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_231:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_232:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_233:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_234:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_235:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_236:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_237:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_238:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_239:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_240:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_241:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_242:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_243:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_244:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_245:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_246:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_247:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_248:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_249:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_250:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_251:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_252:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_253:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_254:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_255:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_256:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_257:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_258:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_259:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_260:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_261:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_262:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_263:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_264:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_265:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_266:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_267:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_268:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_269:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_270:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_271:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_272:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_273:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_274:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_275:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_276:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_277:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_278:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_279:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_280:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_281:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_282:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_283:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_284:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_285:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_286:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_287:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_288:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_289:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_290:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_291:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_292:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_293:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_294:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_295:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_296:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_297:
    .fill 180*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
