
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:03:51 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32D/fcvt.wu.d.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.wu.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.wu.d_b23 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.wu.d_b23)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x8,test_dataset_0)
RVTEST_SIGBASE(x5,signature_x5_1)

inst_0:// rs1==f22, rd==x12,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f22; dest:x12; op1val:0x43dffffffffffffc; valaddr_reg:x8;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x12, f22, dyn, 0, 0, x8, 0*FLEN/8, x13, x5, x3,FLREG)

inst_1:// rs1==f29, rd==x20,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x20 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f29; dest:x20; op1val:0x43dffffffffffffc; valaddr_reg:x8;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x20, f29, dyn, 32, 0, x8, 1*FLEN/8, x13, x5, x3,FLREG)

inst_2:// rs1==f7, rd==x29,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x40 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f7; dest:x29; op1val:0x43dffffffffffffc; valaddr_reg:x8;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x29, f7, dyn, 64, 0, x8, 2*FLEN/8, x13, x5, x3,FLREG)

inst_3:// rs1==f6, rd==x0,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f6; dest:x0; op1val:0x43dffffffffffffc; valaddr_reg:x8;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x0, f6, dyn, 96, 0, x8, 3*FLEN/8, x13, x5, x3,FLREG)

inst_4:// rs1==f30, rd==x6,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x80 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f30; dest:x6; op1val:0x43dffffffffffffc; valaddr_reg:x8;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x6, f30, dyn, 128, 0, x8, 4*FLEN/8, x13, x5, x3,FLREG)

inst_5:// rs1==f15, rd==x9,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f15; dest:x9; op1val:0x43dffffffffffffd; valaddr_reg:x8;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x9, f15, dyn, 0, 0, x8, 5*FLEN/8, x13, x5, x3,FLREG)

inst_6:// rs1==f13, rd==x17,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x20 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f13; dest:x17; op1val:0x43dffffffffffffd; valaddr_reg:x8;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x17, f13, dyn, 32, 0, x8, 6*FLEN/8, x13, x5, x3,FLREG)

inst_7:// rs1==f19, rd==x4,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x40 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f19; dest:x4; op1val:0x43dffffffffffffd; valaddr_reg:x8;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x4, f19, dyn, 64, 0, x8, 7*FLEN/8, x13, x5, x3,FLREG)

inst_8:// rs1==f9, rd==x2,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f9; dest:x2; op1val:0x43dffffffffffffd; valaddr_reg:x8;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x2, f9, dyn, 96, 0, x8, 8*FLEN/8, x13, x5, x3,FLREG)

inst_9:// rs1==f10, rd==x16,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x80 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f10; dest:x16; op1val:0x43dffffffffffffd; valaddr_reg:x8;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x16, f10, dyn, 128, 0, x8, 9*FLEN/8, x13, x5, x3,FLREG)

inst_10:// rs1==f8, rd==x22,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f8; dest:x22; op1val:0x43dffffffffffffe; valaddr_reg:x8;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x22, f8, dyn, 0, 0, x8, 10*FLEN/8, x13, x5, x3,FLREG)

inst_11:// rs1==f11, rd==x28,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x20 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f11; dest:x28; op1val:0x43dffffffffffffe; valaddr_reg:x8;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x28, f11, dyn, 32, 0, x8, 11*FLEN/8, x13, x5, x3,FLREG)

inst_12:// rs1==f31, rd==x19,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x40 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f31; dest:x19; op1val:0x43dffffffffffffe; valaddr_reg:x8;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x19, f31, dyn, 64, 0, x8, 12*FLEN/8, x13, x5, x3,FLREG)

inst_13:// rs1==f21, rd==x11,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f21; dest:x11; op1val:0x43dffffffffffffe; valaddr_reg:x8;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x11, f21, dyn, 96, 0, x8, 13*FLEN/8, x13, x5, x3,FLREG)

inst_14:// rs1==f0, rd==x26,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x80 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f0; dest:x26; op1val:0x43dffffffffffffe; valaddr_reg:x8;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x26, f0, dyn, 128, 0, x8, 14*FLEN/8, x13, x5, x3,FLREG)

inst_15:// rs1==f4, rd==x30,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f4; dest:x30; op1val:0x43dfffffffffffff; valaddr_reg:x8;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x30, f4, dyn, 0, 0, x8, 15*FLEN/8, x13, x5, x3,FLREG)

inst_16:// rs1==f20, rd==x10,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x20 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f20; dest:x10; op1val:0x43dfffffffffffff; valaddr_reg:x8;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x10, f20, dyn, 32, 0, x8, 16*FLEN/8, x13, x5, x3,FLREG)

inst_17:// rs1==f5, rd==x1,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x40 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f5; dest:x1; op1val:0x43dfffffffffffff; valaddr_reg:x8;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x1, f5, dyn, 64, 0, x8, 17*FLEN/8, x13, x5, x3,FLREG)

inst_18:// rs1==f2, rd==x7,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f2; dest:x7; op1val:0x43dfffffffffffff; valaddr_reg:x8;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x7, f2, dyn, 96, 0, x8, 18*FLEN/8, x13, x5, x3,FLREG)

inst_19:// rs1==f3, rd==x25,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x80 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f3; dest:x25; op1val:0x43dfffffffffffff; valaddr_reg:x8;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x25, f3, dyn, 128, 0, x8, 19*FLEN/8, x13, x5, x3,FLREG)

inst_20:// rs1==f24, rd==x27,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f24; dest:x27; op1val:0x43e0000000000000; valaddr_reg:x8;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x27, f24, dyn, 0, 0, x8, 20*FLEN/8, x13, x5, x3,FLREG)

inst_21:// rs1==f27, rd==x31,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f27; dest:x31; op1val:0x43e0000000000000; valaddr_reg:x8;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f27, dyn, 32, 0, x8, 21*FLEN/8, x13, x5, x3,FLREG)

inst_22:// rs1==f12, rd==x14,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f12; dest:x14; op1val:0x43e0000000000000; valaddr_reg:x8;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x14, f12, dyn, 64, 0, x8, 22*FLEN/8, x13, x5, x3,FLREG)

inst_23:// rs1==f1, rd==x21,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f1; dest:x21; op1val:0x43e0000000000000; valaddr_reg:x8;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x21, f1, dyn, 96, 0, x8, 23*FLEN/8, x13, x5, x3,FLREG)

inst_24:// rs1==f25, rd==x15,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f25; dest:x15; op1val:0x43e0000000000000; valaddr_reg:x8;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x15, f25, dyn, 128, 0, x8, 24*FLEN/8, x13, x5, x3,FLREG)
RVTEST_VALBASEUPD(x4,test_dataset_1)

inst_25:// rs1==f14, rd==x18,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f14; dest:x18; op1val:0x43e0000000000001; valaddr_reg:x4;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x18, f14, dyn, 0, 0, x4, 0*FLEN/8, x6, x5, x3,FLREG)

inst_26:// rs1==f17, rd==x8,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f17; dest:x8; op1val:0x43e0000000000001; valaddr_reg:x4;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x8, f17, dyn, 32, 0, x4, 1*FLEN/8, x6, x5, x3,FLREG)

inst_27:// rs1==f23, rd==x3,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f23; dest:x3; op1val:0x43e0000000000001; valaddr_reg:x4;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x3, f23, dyn, 64, 0, x4, 2*FLEN/8, x6, x5, x2,FLREG)
RVTEST_SIGBASE(x1,signature_x1_0)

inst_28:// rs1==f28, rd==x24,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f28; dest:x24; op1val:0x43e0000000000001; valaddr_reg:x4;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x24, f28, dyn, 96, 0, x4, 3*FLEN/8, x6, x1, x2,FLREG)

inst_29:// rs1==f26, rd==x5,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f26; dest:x5; op1val:0x43e0000000000001; valaddr_reg:x4;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x5, f26, dyn, 128, 0, x4, 4*FLEN/8, x6, x1, x2,FLREG)

inst_30:// rs1==f18, rd==x23,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f18; dest:x23; op1val:0x43e0000000000002; valaddr_reg:x4;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x23, f18, dyn, 0, 0, x4, 5*FLEN/8, x6, x1, x2,FLREG)

inst_31:// rs1==f16, rd==x13,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f16; dest:x13; op1val:0x43e0000000000002; valaddr_reg:x4;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x13, f16, dyn, 32, 0, x4, 6*FLEN/8, x6, x1, x2,FLREG)

inst_32:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x4;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 7*FLEN/8, x6, x1, x2,FLREG)

inst_33:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x4;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 8*FLEN/8, x6, x1, x2,FLREG)

inst_34:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x4;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 9*FLEN/8, x6, x1, x2,FLREG)

inst_35:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x4;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 10*FLEN/8, x6, x1, x2,FLREG)

inst_36:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x4;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x4, 11*FLEN/8, x6, x1, x2,FLREG)

inst_37:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x4;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 12*FLEN/8, x6, x1, x2,FLREG)

inst_38:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x4;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 13*FLEN/8, x6, x1, x2,FLREG)

inst_39:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x4;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 14*FLEN/8, x6, x1, x2,FLREG)

inst_40:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x4;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 15*FLEN/8, x6, x1, x2,FLREG)

inst_41:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x4;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x4, 16*FLEN/8, x6, x1, x2,FLREG)

inst_42:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x4;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 17*FLEN/8, x6, x1, x2,FLREG)

inst_43:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x4;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 18*FLEN/8, x6, x1, x2,FLREG)

inst_44:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x4;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 19*FLEN/8, x6, x1, x2,FLREG)

inst_45:// fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43dffffffffffffc; valaddr_reg:x4;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 20*FLEN/8, x6, x1, x2,FLREG)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
.dword 0x43dffffffffffffc
.dword 0x43dffffffffffffc
.dword 0x43dffffffffffffc
.dword 0x43dffffffffffffc
.dword 0x43dffffffffffffc
.dword 0x43dffffffffffffd
.dword 0x43dffffffffffffd
.dword 0x43dffffffffffffd
.dword 0x43dffffffffffffd
.dword 0x43dffffffffffffd
.dword 0x43dffffffffffffe
.dword 0x43dffffffffffffe
.dword 0x43dffffffffffffe
.dword 0x43dffffffffffffe
.dword 0x43dffffffffffffe
.dword 0x43dfffffffffffff
.dword 0x43dfffffffffffff
.dword 0x43dfffffffffffff
.dword 0x43dfffffffffffff
.dword 0x43dfffffffffffff
.dword 0x43e0000000000000
.dword 0x43e0000000000000
.dword 0x43e0000000000000
.dword 0x43e0000000000000
.dword 0x43e0000000000000
test_dataset_1:
.dword 0x43e0000000000001
.dword 0x43e0000000000001
.dword 0x43e0000000000001
.dword 0x43e0000000000001
.dword 0x43e0000000000001
.dword 0x43e0000000000002
.dword 0x43e0000000000002
.dword 0x43e0000000000002
.dword 0x43e0000000000002
.dword 0x43e0000000000002
.dword 0x43e0000000000003
.dword 0x43e0000000000003
.dword 0x43e0000000000003
.dword 0x43e0000000000003
.dword 0x43e0000000000003
.dword 0x43e0000000000004
.dword 0x43e0000000000004
.dword 0x43e0000000000004
.dword 0x43e0000000000004
.dword 0x43e0000000000004
.dword 0x43dffffffffffffc
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x5_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x5_1:
    .fill 56*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_0:
    .fill 36*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
